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Data General's Nova class all shared a common base instruction set. Some later models added a few instructions, mostly concerned with hardware stacks and integer multiply/divide. This page will describe only the basic set.
The Nova architecture defines four 16 bit Accumulators, or AC registers, a 15 bit Program Counter, or PC, and a single bit Carry register. Other basic facets of the machine are two memory pages (either the current page or page zero) and a total of 64 I/O device addresses. Of the four ACs, two may be used as index registers.
Page size in the Nova is 256 words. Addressing is done within the current page using signed arithmetic, hence relative jumps must span no more than 127 addresses. As the PC is always in the center of the current page, jumping across page boundaries isn't a problem.
The Nova specification also states that each I/O device will have three independent buffers available for programming. These are referenced by the letters "A", "B", and "C". Note that not all devices use all three available buffers.
The DG Nova is a 16-bit word machine, the basic word form of which will be represented in this document thusly:
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | +---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
There is no "byte addressing" as such; words are addressed sequentially and bytes are parsed out using swaps and masks high-order byte first. Thus, the Nova is a "big- endian" architecture.
At its' core, the Nova set has 3 basic classes of instructions; these are I/O Instructions, Memory Reference Instructions, and Arithmetic and Logic Instructions. The division of memory access and I/O instructions is in keeping with the fact that the Nova has discrete bus structures for these two functions.
A fourth class of instructions in the CPU Control category could be considered, but these are all I/O instructions directed at the main processor. They do get their own section, however, as do special memory locations.
Depending on which class of instruction is being executed, this word is
broken into various fields, each of which direct the computer's hardware
to perform certain tasks at certain times. In some operations, it is possible
to cause more than one action to be executed with a single instruction.
Input/Output instructions all have the following basic word format:
0 1 1 Transfer /----- Device Code --------\
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ /
AC Control
From this diagram, one can see that to execute an I/O class instruction, bits one and two must be "1" and bit zero must be "0". This is the defining characteristic of the class. Following down the word, the other fields perform the following functions:
Alternately, if the Transfer field contained 111, this field specifies a skip action controlled by the selected device's status. The options are as follows:
Memory access instructions in the Nova fall into two broad classes - instructions which involve an accumulator and those that don't. Those that don't can be divided further into jumps and increment/ decrement instructions. Any of these may use addresses either in the current page or in page zero. Indirection is available for all.
The effective address for all memory- reference instructions is formed using the Displacement field modified by the Index and Indirect options.
The Displacement field is an eight- bit signed quantity taking on a value between 127 and -128.
The Index field acts more like a combined mode/index operator. Basically, if bit 6 is a binary "0", bit 7 acts as a "page switch". Like the PDP-8, the Nova operates with the notion of the "current page" and "page zero". If bit 6 and bit 7 are both "0", a page zero reference is made into the lowest 256 words in memory using the displacement directly as an unsigned address; if bit 6 is a "0" and bit 7 a "1", then the memory reference is made relative to the current PC by algebraically adding the displacement (as a signed value) to the program counter. As the displacement may be negative, it is possible to reference locations "below" the PC in the current page. Toggling bit 6 to a "1" turns on classic indexing in which the value of the displacement field is added to one of two accumulators. Either AC2 or AC3 may be used as an index register with bit 7 determining which of the two is used. The displacement is taken as a signed value in this mode, and as such it is possible to get smaller values than what appears in the indexing AC.
The Indirect bit allows the indirection in which the resulting address from the previous two options is taken as a memory address from which will come the final effective address. That is to say that the value in the first retrieved address is the address of the "true" data. If you're going to be programming these machines, keep this in mind - it took me a while to get it straight.
The basic format for the memory reference without accumulator is:
0 0 0 I /---------- Displacement ----------\
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ /
Function Index
The different functions are as follows:
The different index operations are as follows:
Memory reference instructions that involve accumulators include the LDA and STA operations which load an accumulator from memory and store an accumulator to memory respectively. The basic format for these instructions is as follows:
0 Accumulator Index
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ / \ /
Function I \---------- Displacement -----------/
The Accumulator field can contain a value from 0 to 3 denoting the desired accumulator.
The function field takes on one of two possible values:
The Indirect, Function, and Displacement fields perform identically to
their non- accumulator- reference counterparts.
ALC, or Arithmetic/Logic Class, instructions are distinguished by having a "1" in the bit 0 position.
These instructions allow many things to happen seemingly at once; there are eight "basic" operations that the machine understands, three optional rotate/ swap capabilities, four things that pre-condition the state of the carry bit, and an optional ability to skip the next instruction in sequence depending on the result of an operation. Finally, there is also a single bit that disables the loading of a result into the destination AC.
The basic format of an ALC instruction is:
Destination Shift No
1 Accumulator Control Load
/ \ / \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ / \ / \ /
Source Function Carry Skip
Accumulator Control Control
As in the memory reference with accumulator instructions, the two bit Source and Destination accumulator fields allow the specification of any of the four ACs in the Nova hardware. They may specify the same AC if desired.
The function bits are encoded as follows:
With any of the ALC instructions, it's possible to rotate the result of the operation either one bit to the right or one bit to the left. It is also possible to swap the left and right halves (bytes) of the result. These functions are encoded in the "Shift" field and take on these values:
Before the "Function" is executed, it is possible to set up the condition of the Carry bit to a known quantity. This can take the form of setting it, clearing it, complementing it, or simply ignoring it. The "Carry Control" field is two bits wide and is encoded thusly:
In any of the ALC instructions, it's possible to tell the machine to discard the contents of an operation if the desired aim is merely to test the result for some condition. This is accomplished through use of the "No Load" bit; if said bit is a "1", the result is not loaded into the Destination AC.
Following completion of the "Function" operation, it's possible to test for several possible result conditions. These tests are performed regardless of the state of the "No Load" bit.
If a test "passes", the next sequential instruction in the program is skipped; if the test "fails", the next instruction is executed. There are eight possibilities for skipping, as shown here:
The Nova assembler understands several opcodes as shorthand for certain processor- control functions. These are presented herein in assembler format; they are, without exception, I/O Class instructions. I'll list the equivalent I/O construct with each.
While not overly reliant on dedicated memory locations and so- called "magic numbers", the Nova does allocate some memory locations for special uses. Most notable of these are the locations between 20 and 37 (octal) and locations 0 and 1.
Locations 20 through 37 are special in that when they are accessed as part of an indirect operation, they increment or decrement their contents before the effective address is calculated. This makes them useful for traversing tables and large chunks of memory. The locations 20 through 27 are auto- increment locations which increment their contents by one before the value is used; locations 30 through 37 are auto- decrement in that they decrement their value by one before the value is taken. The locations behave normally for non- indirect accesses.
Locations 0 and 1 are used by the machine's program interrupt facility. When an interrupt occurs, the continuation address (the PC before interrupt) is placed into location zero and the machine executes an indirect jump through location one. Hence, location 1 must contain the start address of the interrupt handler. When an interrupt happens, further interrupts are disabled until they are explicitly re-enabled. A return from the interrupt is performed by jumping indirectly through location zero (i.e. JMP @0).
Nova assembly language looks substantially similar to other assemblers in that it has labels, opcodes, and options.
For the most part, opcodes are made up of a concatenation of the basic function and whatever options are attached to said function. For instance INCZL 0,1,SZC sets the carry bit to zero, increments the contents of AC1, rotates the result left one bit, places the resulting value into AC0, tests the carry bit, and skips the next instruction if carry is zero. As a second example, LDA 3, @5 loads AC3 with the data from the address specified in location 5 (indirect addressing).
As shown in the previous example, the indirect bit is specified by a '@' character. The "No Load" bit is denoted with a '#' character. Note that either of these may occur anywhere on a line (e.g. LDA@ 3,5 performs the same load as the previous example). A "No Load" notation appears thusly: SUB# 0,1,SZR. This example tests AC0 and AC1 for equality, preserves the contents of both ACs, and skips the next instruction if the two are equal.
The current memory location in Nova assembler is denoted with a '.' (period) character as in: JMP .+5 which jumps forward 5 memory addresses. Note, that unlike the pdp11 this is the current PC not the incremented one, hence JMP . is a self- jump and a JMP .+1 is a no-op.
As in most other assemblers out there, comments are begun with a ';' (semicolon) character and cause the rest of the line to be ignored.
What's Nova assembler look like, you ask? Have a look at a listing for the Nova "program load" sequence.
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Last Modified: Sun Sep 13 09:01:59 EDT 1998