Data General NOVA ®
CPU Control Instructions

    This page describes the instructions which are used to control the internal operation of the CPU and various devices attached to it.

    Coverage of the Nova CPU would be lacking if it left out how the CPU controls itself and its peripherals through its programming. This page will set forth the was that this is done.

    These instructions all function as I/O instructions which are targetted at the CPU, device number 77. Since that's the case, the instruction format is an I/O one:

       0 1 1             Transfer           /----- 1 1 1 1 1 1 --------\
   /           \       /          \        /                            \
   | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
               \      /            \       /
                  AC                Control

    The OPcode of each CPU control instruction is specified by its function and is defined by the ``Transfer'' and ``Control'' fields above. Instructions will be shown by their OPcode. It should be noted that these are really pseudo- operations, as the assembler translates them into the requisite I/O instructions.

    On a hardware level, the CPU ``Busy'' flag controls the status of the interrupt system and the ``Done'' flag is a power- failure indicator.

The Instructions

I/O Reset (IORST)

Equivalent I/O instruction: DICC  0, CPU
   The IORST instruction issues an I/O bus reset which causes all devices attached to the I/O bus to reset. All devices are left in a predefined, usually a "power-on", condition.

Assembler Syntax:

Start:    PC=50, I/O bus undefined
Function: IORST
Finish:   PC=51, I/O bus reset


Equivalent I/O instruction: DOC  0, CPU
   The HALT instruction stops the computer by turning off the ``RUN ''flag in the processor status logic. The PC is set to the next sequential instruction. Pressing the ``Continue'' switch on the front panel resumes execution. No ACs or I/O devices are affected.

Assembler Syntax:

Start:    PC=505, CPU running
Function: HALT
Finish:   PC=506, CPU halted

Read Panel Switches (READS)

Equivalent I/O instruction: DIA  AC, CPU
   The READS instruction reads the contents of the front- panel switches and places said data into the specified AC. The previous contents of the AC are lost.

Assembler Syntax:

Start:    Panel Switches=172000, AC1=0, PC=75
Function: READS  1
Finish:   AC1=172000, PC=76

Enable I/O Interrupts (INTEN)

Equivalent I/O instruction: NIOS  0, CPU
   The INTEN instruction causes the CPU to enable its interrupt system following the next instruction. This, in turn, allows I/O devices to interrupt the normal instruction flow by raising a flag in the CPU.

Assembler Syntax:

Start:    PC=3512, Interrupts disabled
Function: INTEN
Finish:   PC=3513, Interrupts enabled (at 3514 assuming no jump)

Disable I/O Interrupts (INTDS)

Equivalent I/O instruction: NIOC  0, CPU
   The INTDS instruction immediately disables the I/O interrupt system, thereby preventing devices from altering the CPU's execution path.

Assembler Syntax:

Start:    PC=3176, Interrupts enabled
Function: INTDS
Finish:   PC-3177, Interrupts disabled

Set Interrupt Mask (MSKO)

Equivalent I/O instruction: DOB   AC, CPU
   The MSKO instruction places the contents of the selected AC into the interrupt mask registers of all the interrupt- capable devices on the I/O bus. The AC is not altered.

Assembler Syntax:

Start:    PC=2176, AC2=157200, Interrupt mask=157300
Function: MSKO  2
Finish:   PC=2177, AC2=157200, Interrupt mask=157200

Acknowledge Interrupt (INTA)

Equivalent I/O instruction: DIB   AC, CPU
   The INTA instruction acknowledges an interrupt by placing the interrupting device's address into the selected AC. The previous contents of the AC are lost.

Assembler Syntax:

Start:    PC=312, Device 27 interrupting, Interrupts on
Function: INTA 3
Finish:   PC=313, AC3=27, Device 27 interrupt active, Interrupts off

    This page described the Input/Output instructions of the Data General Nova minicomputer. Other pages describe:

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Copyright © 1998 - 2003, Carl R. Friend. All rights reserved.

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Last Modified: Sun Sep 13 15:15:46 EDT 1998