Certain late- model Novas, and the MicroNOVA class machines have certain features that distinguish them from the earlier machines. Most notably these include stack instructions, hardware multiply/ divide, and, in the Nova 4, byte manipulation and trap capabilities. Late model Novas also have additional dedicated memory locations above and beyond earlier systems.
These extended abilities were implemented using I/O instructions pointing to device number one - the Multiply/ Divide device in the early Novas. Hence, all the instructions presented here will use the standard I/O form of:
0 1 1 Transfer /----- Device Code --------\
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ /
AC Control
I'm not going to detail all the possible bit positions using the above diagram, but am going to describe the instructions using the assembler format. Refer to the basic I/O instruction document for bit coding of the individual options.
First, let's have a look at the multiply/ divide instructions. These were optional on most of the early Nova- class machines but became standard on the MicroNOVAs.
AC0 is special in this case, as the instruction takes the 16 high- order
bits of the multiplication result and adds them into AC0.
Machines commencing with the Nova 3 sport hardware stacks, as do the members of the MicroNOVA family. These facilities greatly ease the handling of subroutines and facilitate the writing of re-entrant code. Basic capabilities like Push and POP are supported as well as some more advanced features. I'll discuss each in turn.
All the stack instructions are, in fact, translated into I/O instructions by the assembler. The device number for all of them is 1 - the same as for the optional hardware multiply/ divide.
Once the return block is pushed, the machine loads the updated contents of the stack pointer into the Frame pointer and AC3.
NOTE: The SAVe instruction is intended to be called immediately following the execution of a JSR instruction and entry into a subroutine. At this point in time, AC3 will contain the return address for the subroutine.
The assembler interprets the SAV as a DIC AC,1 I/O instruction.
Once the block is popped, the instruction loads the updated contents of AC3 into the Frame Pointer. Program execution continues from the PC value loaded from the stack.
The assembler interprets the RET as a DICC AC,1 I/O instruction.
Memory integrity is protected from runaway stacks by the stack protection mechanism. This facility causes a trap to location 3 in page zero when the stack pointer is incremented (or decremented) across a page boundary.
When a stack fault occurs, the address of the offending instruction is placed into page zero location 0 and the processor executes an indirect jump through page zero address 3. This is essentially the same as a standard Nova interrupt. Note that interrupts must be enabled for a stack fault to occur.
Beginning with the Nova 4, machines began to include byte- pointer instructions thereby lessening the burden on programmers by allowing them to forget about swapping bytes within words (remember that the NOVA is word addressed and accessed, not byte addressed). Like the stack instructions, these resemble I/O instructions addressed to device one.
The byte pointers used in these instructions are compatible with the the older style ones, which is to say that the pointer is formed by taking the word address, shifting it left one bit position thereby leaving bit 15 to specify which byte is to be manipulated.
There are two byte manipulation instructions, LDB and STB which will be described here. The instructions appear in memory in this format:
001 or 100
0 1 1 LDB STB 0 0 0 0 0 1
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ /
ACD ACS
The assembler codes the instruction as DIA ACD, and puts the ACS specifier into the Transfer field. See the above diagram.
The assembler codes the instruction as DOB ACD, and puts the ACS specifier into the Transfer field. See the above diagram.
In a bow the Eclipse line, and in recognition that the machine classes were close enough to one another that programs written on the Nova class could execute natively on the Eclipse machines, the Nova 4 included the trap instruction designed to catch Eclipse- specific instructions. Creative programmers could use this facility to emulate lots of the Eclipse instructions on a Nova 4 if they so desired. The instruction appears thusly in memory:
1 ACD 1 0 0 0
/ \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+----+
\ / \ /
ACS Trap Number
The observent reader should note that this is an ALC instruction with the no-load bit set and the never skip option selected. This is a combination which normally would never occur in general usage as it serves no function, other than as a no-op. It gets coded as follows:
In addition to the standard Nova interrupt locations 0 and 1 in page zero, the extended Novas reserve three other words for trap purposes. These are:
The first was discussed in the previous section on stack instructions. The second two reflect the direction that the 16- bit DG line was taking at the time and presage the coming of the Eclipse extended instructions.
In the later Nova processors, if an ALC instruction is encountered that
has the "No Load" bit set AND has a "never skip" option
coded into it the machine assumes that the instruction is an Eclipse
construct and traps, first storing the address of the offending instruction
in location 46 then jumping indirectly through location 47.
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Last Modified: Sun Jul 5 10:53:50 EDT 1998