Each instruction that the Interdata machine understands will be presented below. Where instructions may be of more than one type (e.g. RR, RX, RS), they will be grouped together. Note that some instructions are only valid on machines with appropriate options - this is especially true of the multiply/ divide and floating- point operations.
In general, instructions will be presented by their assembler mnemonics, followed by their class and hexidecimal operation code (opcode). Notes about each instruction's operational characteristics will be presented where appropriate and any effects upon the PSW or CC bits will be discussed.
This page describes the branch instructions in the Interdata set. Other pages describe:
The Branch on True Condition instruction tests the status of the condition flags by logically ANDing them with the contents of the M1 field. If the result of the AND operation is non- zero, program execution passes to the location specified by the second operand. If the test fails (i.e. the AND operation returns zero), execution continues either at PC+2 (for the RR class instruction) or at PC+4 (for the RX instruction).
See the "extended" OPcodes for examples.
Notes:
None of the CC bits are altered during the execution of this instruction.
The Branch on False Condition instruction tests the status of the condition flags by logically ANDing them with the contents of the M1 field. If the result of the AND operation is zero, program execution passes to the location specified by the second operand. If the test fails (i.e. the AND operation returns non- zero), execution continues either at PC+2 (for the RR class instruction) or at PC+4 (for the RX instruction).
See the "extended" OPcodes for examples.
Notes:
None of the CC bits are altered during the execution of this instruction.
The Branch unconditional instruction loads the PC (PSW[16:31]) with the value of the second operand. Program execution continues from that point.
Notes:
The Branch unconditional instruction is a special form of the Branch on False Condition operation where the test is guaranteed to be satisfied.
The NOP instruction loads the PC (PSW[16:31]) with the value of the the PC + 2 (for the RR construct) or the PC + 4 (for the RX construct). point.
Notes:
The NOP is a special form of the Branch on True condition instruction where the test is guaranteed to fail. It is usually used as a "place holder" in code which may need patching later.
The Branch on Index High instruction uses three contiguous GPRs with the following contents (all of which may be signed):
The instruction takes the value (R1+1) and adds it to (R1), places the result into (R1), and then logically compares (R1) to (R1+2). If the comparison indicates that (R1) are less than, or equal to, (R1+2) (PSW[16:31]) get A + (X2), otherwise (PSW[16:31]) get (PSW[16:31]) + 4.
Notes:
The comparison operation of this instruction is unsigned.
The highest GPR that can be used in this instruction is 13, as the top GPR is 15.
The Branch on Index Low or Equal instruction uses three contiguous GPRs with the following contents (all of which may be signed):
The instruction takes the value (R1+1) and adds it to (R1), places the result into (R1), and then logically compares (R1) to (R1+2). If the comparison indicates that (R1) are less than, or equal to, (R1+2) (PSW[16:31]) get (PSW[16:31]) + 4, otherwise (PSW[16:31]) get A + (X2).
Notes:
The comparison operation of this instruction is unsigned.
The highest GPR that can be used in this instruction is 13, as the top GPR is 15.
The Branch and Link instructions cause the current value of the PC (PSW[16:31]) + 2 (for the RR form) or 4 (for the RX form) to be placed in (R1) and (PSW[16:31]) to receive (R2) (RR form) or A + (X2) (RX form).
Notes:
Used for calling subroutines.
For the convenience of programmers working with Interdata computers, an "extended" set of mnemonics is defined in the assembler to assist with the most commonly used branches. They all translate to either a BTC or BFC instruction and set the test mask appropriately.
In all the instruction synopses below, the action shows the "test satisfied"
condition; if the test fails, the action is
(PSW[16:31]) <-- (PSW[16:31]) + 4.
The Branch on Zero instruction tests the G and L bits of the PSW. If both these bits are zero, the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BZ instruction is translated to a "BFC 3" by the assembler.
The Branch on Not Zero instruction tests the G and L bits of the PSW. If either of these bits are one, the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BNZ instruction is translated to a "BTC 3" by the assembler.
The Branch on Plus instruction tests the G bit of the PSW. If this bit is a one the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BP instruction is translated to a "BTC 2" by the assembler.
The Branch on Not Plus instruction tests the G bit of the PSW. If this bit is a zero the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BNP instruction is translated to a "BFC 2" by the assembler.
The Branch on Minus instruction tests the L bit of the PSW. If this bit is a one the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BM instruction is translated to a "BTC 1" by the assembler.
The Branch on Not Minus instruction tests the L bit of the PSW. If this bit is a 0 the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BNM instruction is translated to a "BFC 1" by the assembler.
The Branch on Carry instruction tests the C bit of the PSW. If this bit is a 1 the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BC instruction is translated to a "BTC 8" by the assembler.
The Branch on Overflow instruction tests the V bit of the PSW. If this bit is a 1 the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BO instruction is translated to a "BTC 4" by the assembler.
The Branch on Overflow instruction tests the C bit of the PSW. If this bit is a 1 the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BL instruction is translated to a "BTC 8" by the assembler.
This instruction is only useful following a CLH or CE instruction.
The Branch on Not Low instruction tests the V bit of the PSW. If this bit is a 0 the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BNL instruction is translated to a "BFC 8" by the assembler.
This instruction is only useful following a CLH or CE instruction.
The Branch on Equal instruction tests the G and L bits of the PSW. If these bits are both zero the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BE instruction is translated to a "BFC 3" by the assembler.
This instruction is only useful following a CLH or CE instruction.
The Branch on Equal instruction tests the G and L bits of the PSW. If either of these bits are a one the instruction branches; if not, the instruction continues seqential execution.
Notes:
The BNE instruction is translated to a "BTC 3" by the assembler.
This instruction is only useful following a CLH or CE instruction.
This page described the branch class instructions in the Interdata set. Other pages describe:
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Last Modified: Sat May 13 13:04:15 EDT 2000