 # Interdata Instruction SetLoad/Store Types ## Instructions

Each instruction that the Interdata machine understands will be presented below. Where instructions may be of more than one type (e.g. RR, RX, RS), they will be grouped together. Note that some instructions are only valid on machines with appropriate options - this is especially true of the multiply/ divide and floating- point operations.

In general, instructions will be presented by their assembler mnemonics, followed by their class and hexidecimal operation code (opcode). Notes about each instruction's operational characteristics will be presented where appropriate and any effects upon the PSW or CC bits will be discussed.

This page describes the Load/Store instructions in the Interdata set. Other pages describe:

```LH  R1, A(X2) - [RX] - 0x48 | (R1) <-- [(X2) + A]
LHI R1, A(X2) - [RS] - 0xC8 | (R1) <-- (X2) + A
LHR R1, R2    - [RR] - 0x08 | (R1) <-- (R2)
```

The Load Halfword instruction is used to load one sixteen bit halfword from memory into a GPR, or to move one halfword from one GPR to another.

Affected CC bits:

```	C V G L
-------
0 0 - Operand is zero
0 1 - Operand is Less than zero
1 0 - Operand is Greater than zero
```

Notes:

The LHI instruction produces a result that is the algebraic sum of the contents of GPR X2 and the value of A.

#### Store Halfword

```STH  R1, A(X2) - [RX] - 0x40 | [(X2) + A] <-- (R1)
```

The Store Halfword operation is used to store the contents of a GPR into main memory. This operation is only available in the RX format.

Affected CC bits:

```	None.
```

```LB  R1, A(X2) - [RX] - 0x93 | (R1[8:15]) <-- [(X2) + A], (R1[0:7] <-- ZERO
LBR R1, R2    - [RR] - 0xD3 | (R1[8:15]) <-- (R2[8:15]), (R1[0:7] <-- ZERO
```

The right- hand byte of the source is loaded into the right- hand byte of the destination and the left- hand byte of the destination is set to zero.

Affected CC bits:

```	None.
```

#### Store Byte

```STB  R1, A(X2) - [RX] - 0x92 | [(X2) + A] <-- (R1[8:15])
STBR R1, R2    - [RR] - 0xD2 | (R2[8:15]) <-- (R1[8:15])
```

The right- hand byte of the source GPR is stored into main memory or the target GPR. In the case of a GPR destination, the left- hand byte remains untouched.

Affected CC bits:

```	None.
```

```LM  R1, A(X2) - [RX] - 0xD1 | See below.
```

Sequential GPRs with increasing addresses (to 15), beginning with the GPR specified in field R1, are loaded from sequentially increasing memory halfwords beginning with the effective address. Up to all 16 GPRs may be loaded in this manner.

The operation of this command may be summarised thusly:

```	t := R1;
do {
(Rt) <-- [(X2 + A + 2*t]
} while t <= 0xF;
```

Affected CC bits:

```	None.
```

Notes:

This instruction does not exist on the Model 3 and may be optional on other models.

#### Store Multiple

```STM  R1, A(X2) - [RX] - 0xD0 | See below.
```

Sequential GPRs with increasing addresses (to 15), beginning with the GPR specified in field R1, are stored into main memory at increasing halfword addresses beginning with the effective address. Up to all 16 GPRs may be saved in this manner.

The operation of this command may be summarised thusly:

```	t := R1;
do {
[(X2 + A + 2*t] <-- (Rt)
} while t <= 0xF;
```

Affected CC bits:

```	None.
```

Notes:

This instruction does not exist on the Model 3 and may be optional on other models.

#### Floating Point Load

```LE  R1, A(X2) - [RX] - 0x28 | (R1) <-- [(X2) + A]
LER R1, R2    - [RR] - 0x68 | (R1) <-- (R2)
```

The source floating- point operand is normalised and placed into the destination GPR. A number is considered normalised if the left- most hexidecimal group of bits is non- zero. If the left- most group is zero, the source operand is left- shifted 4 bits and the exponent is decremented by one. If such normalisation causes an exponent underflow, the entire word os set to zero and the overflow (V) CC bit is set.

Affected CC bits:

```	C V G L
-------
0 0 - Operand is Zero
0 1 - Operand is Negative
1 0 - Operand is Greater than zero
1     - An underflow occurred during normalisation
```

Notes:

This instruction does not exist on the Model 3 and may be optional on other models.

#### Floating Point Store

```STE  R1, A(X2) - [RX] - 0x60 | [(X2) + A] <-- (R1)
```

The floating point register specified by R1 is placed into main memory at the effective address. This is a fullword operation.

Affected CC bits:

```	None.
```

Notes:

This instruction does not exist on the Model 3 and may be optional on other models.

#### Load Program Status Word

```LPSW  A(X2) - [RX] - 0xC2 | (PSW[0:31]) <-- [(X2) + A]
```

The 32 bit Program Stats Word is loaded from the effective address.

Affected CC bits:

```	Determined by loaded word.
```

```AL  R1,A(X2) - [RX] - 0xD5 | See below
```

The Autoload instruction initiates a memory load from a byte- oriented I/O device specified in memory location 0x78 using the I/O command specified in memory address 0x79. The load commences at memory location 0x80 with the first non- zero data byte retrieved from the device and continues until the effective address is reached.

Affected CC bits:

```	C V G L
-------
0 0 0 0 - Data transfer completed successfully
1       - Device busy
1     - Examine device status
1   - End of medium on device
1 - Device unavailable
```

Notes:

This instruction does not exist on the Model 3 and may be optional on other models.

This page described the Load/Store instructions in the Interdata set. Other pages describe: [ Museum Lobby ] [ Museum Catalogue ] [ Carl's Homepage ]

Comments to: carl.friend@rcsri.org 