Interdata Instruction SetLogical Instruction Types

Instructions

Each instruction that the Interdata machine understands will be presented below. Where instructions may be of more than one type (e.g. RR, RX, RS), they will be grouped together. Note that some instructions are only valid on machines with appropriate options - this is especially true of the multiply/ divide and floating- point operations.

In general, instructions will be presented by their assembler mnemonics, followed by their class and hexidecimal operation code (opcode). Notes about each instruction's operational characteristics will be presented where appropriate and any effects upon the PSW or CC bits will be discussed.

This page describes the logic class instructions in the Interdata set. Other pages describe:

Logical Instructions

AND Halfword

```NH  R1, A(X2) - [RX] - 0x44 | (R1) <-- (R1) .AND. [(X2) + A]
NHI R1, A(X2) - [RS] - 0xC4 | (R1) <-- (R1) .AND. (X2) + A
NHR R1, R2    - [RR] - 0x04 | (R1) <-- (R1) .AND. (R2)
```

The AND Halfword instruction takes the logical product (the Boolean AND function) of the first and second operands and places the result into R1. This is a bit- wise operation.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is Not zero
1 0 - Result is Not zero
```

Notes:

The logical AND function is represented by the truth table below:

```	X  Y  |  Q
----------
0  0     0
0  1     0
1  0     0
1  1     1
```

OR Halfword

```OH  R1, A(X2) - [RX] - 0x46 | (R1) <-- (R1) .OR. [(X2) + A]
OHI R1, A(X2) - [RS] - 0xC6 | (R1) <-- (R1) .OR. (X2) + A
OHR R1, R2    - [RR] - 0x06 | (R1) <-- (R1) .OR. (R2)
```

The OR Halfword instruction performs a Boolean OR function between the first first and second operands and places the result into R1. This is a bit- wise operation.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is Not zero
1 0 - Result is Not zero
```

Notes:

The logical OR function is represented by the truth table below:

```	X  Y  |  Q
----------
0  0     0
0  1     1
1  0     1
1  1     1
```

Exclusive OR Halfword

```XH  R1, A(X2) - [RX] - 0x47 | (R1) <-- (R1) .XOR. [(X2) + A]
XHI R1, A(X2) - [RS] - 0xC7 | (R1) <-- (R1) .XOR. (X2) + A
XHR R1, R2    - [RR] - 0x07 | (R1) <-- (R1) .XOR. (R2)
```

The Exclusive OR Halfword instruction performs a Boolean exclusive OR function between the first first and second operands and places the result into R1. This is a bit- wise operation.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is Not zero
1 0 - Result is Not zero
```

Notes:

The logical exclusive OR function is represented by the truth table below:

```	X  Y  |  Q
----------
0  0     0
0  1     1
1  0     1
1  1     0
```

Compare Halfword

```CLH  R1, A(X2) - [RX] - 0x45 | (R1) - [(X2) + A]
CLHI R1, A(X2) - [RS] - 0xC5 | (R1) - (X2) + A
CLHR R1, R2    - [RR] - 0x05 | (R1) - (R2)
```

The Compare Halfword instruction compares the contents of the first and second operands and sets the CC bits accordingly. Neither operand is altered.

Affected CC bits:

```	C V G L
-------
0 0 - Operands are Equal
0 1 - Operands are Not Equal
1 0 - Operands are Not Equal
1       - First operand less than second operand
0       - First operand equal to or greater than second
```

Floating- Point Compare

```CE  R1, A(X2) - [RX] - 0x29 | (R1) - [(X2) + A]
CER R1, R2    - [RR] - 0x69 | (R1) - (R2)
```

The Floating- Point Compare instruction compares the contents of the first and second operands and sets the CC bits accordingly. Neither operand is altered. The comparison is based on the rules of algebra and takes into account sign, exponent, and mantissa.

Affected CC bits:

```	C V G L
-------
0 0 - Operands are Equal
0 1 - Operands are Not Equal
1 0 - Operands are Not Equal
1       - First operand less than second operand
0       - First operand equal to or greater than second
```

Notes:

The Floating- Point Compare instruction is an optional instruction and may not appear on all machines.

Shift Left Halfword Arithmetic

```SLHA  R1, A(X2) - [RS] - 0xCF | See below
```

The Shift Left Halfword Arithmetic instruction shifts the value contained in R1 left by the number specified by the sum of X2 and the Address field. The shift involves bits 1 - 15; bit 0, the sign, is left untouched. The Carry bit receives the contents of bit one following the shifting operation; zeroes are shifted into bit 15.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is less than zero
1 0 - Result is greater than zero
0       - The last bit shifted out was a "0"
1       - The last bit shifted out was a "1"
```

Notes:

The ASHL instruction is useful for integer multiplying a number by a power of two. Shifting by one bit position is equivalent to multyplying by two, two bit positions, by four, etc.

Shift Right Halfword Arithmetic

```SRHA  R1, A(X2) - [RS] - 0xCE | See below
```

The Shift Right Halfword Arithmetic instruction shifts the value contained in R1 right by the number specified by the sum of X2 and the Address field. The shift involves bits 1 - 15; bit 0, the sign, is left untouched. The Carry bit receives the contents of bit 15 following the shifting operation; zeroes are shifted into bit 1.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is less than zero
1 0 - Result is greater than zero
0       - The last bit shifted out was a "0"
1       - The last bit shifted out was a "1"
```

Notes:

The ASHL instruction is useful for integer dividing a number by a power of two. Shifting by one bit position is equivalent to dividing by two, two bit positions, by four, etc.

Shift Left Logical Halfword

```SLHL  R1, A(X2) - [RS] - 0xCD | See below
```

The Shift Left Logical Halfword instruction shifts the value contained in R1 left by the number specified by the sum of X2 and the Address field. The shift involves all 16 bits of the halfword. The Carry bit receives the contents of bit 0 following the shifting operation; zeroes are shifted into bit 15.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is less than zero
1 0 - Result is greater than zero
0       - The last bit shifted out was a "0"
1       - The last bit shifted out was a "1"
```

Shift Right Logical Halfword

```SRHL  R1, A(X2) - [RS] - 0xCC | See below
```

The Shift Right Logical Halfword instruction shifts the value contained in R1 right by the number specified by the sum of X2 and the Address field. The shift involves all 16 bits of the halfword. The Carry bit receives the contents of bit 15 following the shifting operation; zeroes are shifted into bit 0.

Affected CC bits:

```	C V G L
-------
0 0 - Result is zero
0 1 - Result is less than zero
1 0 - Result is greater than zero
0       - The last bit shifted out was a "0"
1       - The last bit shifted out was a "1"
```

This page described the logic class of instructions in the Interdata set. Other pages describe:

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