Each instruction that the Interdata machine understands will be presented below. Where instructions may be of more than one type (e.g. RR, RX, RS), they will be grouped together. Note that some instructions are only valid on machines with appropriate options - this is especially true of the multiply/ divide and floating- point operations.
In general, instructions will be presented by their assembler mnemonics, followed by their class and hexidecimal operation code (opcode). Notes about each instruction's operational characteristics will be presented where appropriate and any effects upon the PSW or CC bits will be discussed.
This page describes the arithmetic instructions in the Interdata set. Other pages describe:
The Add Halfword instruction algebraically adds the two operands together to produce the sum of the two. All operands are signed 16 bit quantities.
Affected CC bits:
C V G L
-------
0 0 - Sum is zero
0 1 - Sum is Less than zero
1 0 - Sum is Greater than zero
1 - Result caused Overflow
1 - Result caused a Carry
Notes:
The Add Halfword Immediate instruction produces a result which consists of the algebraic sum of the contents of R1, X2, and the Address Field.
The Add Halfword with Carry instruction algebraically adds the two operands together to produce the sum of the two including the current status of the Carry bit. The two GPRs are 16 bit quantities; Carry is a single bit.
Affected CC bits:
C V G L
-------
0 0 - Sum is zero
0 1 - Sum is Less than zero
1 0 - Sum is Greater than zero
1 - Result caused Overflow
1 - Result caused a Carry
Notes:
The Add Halfword with Carry instruction is used in the implementation of multiple- precision arithmetic. The basic stategy is to add the lower- order operands then for each next- higher order set use the ACH instruction to include the carry out of the previous (lower- order) calculation.
The Subtract Halfword instruction algebraically subtracts the contents of the second operand from the first and places the result into the former.
Affected CC bits:
C V G L
-------
0 0 - Difference is zero
0 1 - Difference is Less than zero
1 0 - Difference is Greater than zero
1 - Result caused Overflow
1 - Result caused a Borrow
Notes:
The Subtract Halfword Immediate instruction produces a result which consists of the algebraic difference of the contents of R1 and the sum of X2 and the Address Field.
The Subtract Halfword with Carry instruction algebraically subtracts the contents of the second operand from the first, subtracts the value of the Carry bit from that, and then places the result into the former.
Affected CC bits:
C V G L
-------
0 0 - Difference is zero
0 1 - Difference is Less than zero
1 0 - Difference is Greater than zero
1 - Result caused Overflow
1 - Result caused a Borrow
Notes:
This instruction is used in multiple- precision arithmetic. For details, see the Add Halfword with Carry instruction.
The Multiply Halfword instruction multiplies the signed value in (R1 + 1) by the quantity in the second operand. The high- order 15 bits (plus sign) of the result are stored in R1; the low- order 16 bits are placed into (R1 + 1). The second operand is unchanged during the operation.
Affected CC bits:
None.
Notes:
General Purpose Register (GPR) R1 must be an even- numbered register during this operation.
This instruction is optional on early- model Interdata machines.
Execution of the Divide Halfword instruction causes the quotient of the 32- bit dividend in R1 and R1+1 and the 16- bit divisor in the second operand to be placed into R1+1. R1 receives the remainder of the division.
Affected CC bits:
None.
Notes:
The first operand (R1) must be an even- numbered register.
This instruction is optional on early- model Interdata machines.
The Floating point instruction set was not avalilable on the early- model Interdata machines and may have been optional on later- model ones.
Interdata's Floating Point instructions operate on 32-bit quantities, of which 1 bit is taken up with sign information, 7 bits represent the exponent (in excess 64 notation), and 24 bits of mantissa (or fraction).
The Interdata Floating Point format does not use the IEEE standard in that numbers in the Interdata format are considered normalised if the high- order hexadecimal digit of the mantissa is non-zero. The exponent, in this format, increments or decrements in conjunction with 4-bit shifts in the mantissa.
That having been said, I must admit that I really don't have a detailed grasp of the intracies of floating- point maths on computers, never having needed to use the facility outside of high- level languages.
The Floating Point Add instruction adds the two operands together to produce the sum of the two. Operands are normalised before the addition, and are post- normalised following the addition.
Affected CC bits:
C V G L
-------
0 0 - Sum is zero
0 1 - Sum is Less than zero
1 0 - Sum is Greater than zero
1 - Exponent Overflow or Underflow
The Floating Point Subtract instruction subtracts the second operand from the first operand and stores the result in R1. Operands are normalised before the subtraction, and are post- normalised following the subtraction.
Affected CC bits:
C V G L
-------
0 0 - Difference is zero
0 1 - Difference is Less than zero
1 0 - Difference is Greater than zero
1 - Exponent Overflow or Underflow
The Floating Point Multiply instruction multiplies the first and second operands and stores the product in R1. Operands are normalised before the multiplication, and are post- normalised following it.
Affected CC bits:
C V G L
-------
0 0 - Product is zero
0 1 - Product is Less than zero
1 0 - Product is Greater than zero
1 - Exponent Overflow or Underflow
The Floating Point Divide instruction divides the first by the second operand and stores the product in R1. Operands are normalised before the division, and are post- normalised following it.
Affected CC bits:
C V G L
-------
0 0 - Quotient is zero
0 1 - Quotient is Less than zero
1 0 - Quotient is Greater than zero
1 - Exponent Overflow or Underflow
This page described the arithmetic instructions in the Interdata set. Other pages describe:
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Last Modified: Sat May 13 13:04:15 EDT 2000