Interdata
Quick Summary

Foreward

This document will attempt to describe the Interdata line of 16 bit computers, at least up to the Model 4, in sufficient detail to allow a hobbyist to begin to program the device at a machine- code level.

The document is not intended to be an in- depth analysis of the machine, nor is it intended to be a tutorial on programming the device. I've prepared it primarily as an aid to hobbyists who may have acquired one of these systems and who wish to use said system as an amusement or part of a working collection. I've tried to be as accurate as possible, but I'm sure there are errors and as my personal Interdata machine is currently non- operational I haven't been able to verify some of the quirks I've found in the official documentation, from which this is derived.

This document is arranged in sections which cover:

Architecture

The Interdata 16 bit machines, of which several models were manufactured, share a common architecture and instruction- set at the user- program level. This is characterised by a 16- bit ALU width, an architectural maximum size of 65,536 bytes of mainstore, and 16 General Purpose Registers. Of the 16 GPRs, 15 may be used as index registers for address modification.

The machine sports a 32- bit Processor Status Word (PSW) which consists of the 16 bit Program Counter (PC), the current Condition Codes (CC), and assorted machine status bits. This register will be described later.

I/O in the Interdata machines is performed in 8-bit bytes whilst operating under program control. A 16-bit direct memory access channel is provided for special high- speed peripherals and those which require full 16 bit words.

Interdata uses the IBM notion of "Halfword" to denote a sixteen bit quantity and "Fullword" to describe a 32 bit value. The term "Byte" is used for an eight bit quantity.

Data alignment is important in the Interdata machines. While bytes may begin on any valid address, halfwords must begin only on even addresses, and fullwords must begin only on addresses which are a multiple of four. Hence, we may make the following table of valid starting addresses:

     Low
   Address:   0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
----------------------------------------------------------------
   Byte       X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X
   Halfword   X     X     X     X     X     X     X     X
   Fullword   X           X           X           X

The mainstore in the Interdata machines operates on a halfword- by- halfword basis, 16 bits at a time. This means that for byte- level accesses, a 16 bit quantity is taken from memory, and, in necessary, shifted/ masked to provide the eight bit byte. The reverse is true for writing bytes to memory.

Numbering within the machine is done in hexidecimal (base 16) to ease the task of binary conversions. The assembler mnemonics bear a strong resemblance to IBM's Basic Assembler Language (BAL) from the 1960s. Note that while the bit- order seems to define the Interdata machines as "big- endian", they are, in fact, "little- endian" in that they order bytes from low to high in sequential addresses.

Addressing Modes

The Interdata machines support three addressing modes, known as Register- to- Register (RR), Register- to- Indexed-Storage (RX), and Register- to- Storage (RS). Indirect addressing, interestingly enough, is not supported in the basic machine. The three modes are described below and will introduce some of the concepts used in later instruction- by- instruction descriptions. All instructions have a common eight bit "OP-Code" (OPeration Code); other fields vary according to instruction format.

RR - Register-to-Register

The RR mode is used where it is desired to pass a halfword (16 bits) from one GPR to another without involving main memory. RR format instructions are one halfword in length, must begin on even addresses, and take on the following format:

   |0             7|8    11|12   15|
   +---------------+-------+-------+
   |    OP-Code    |  R1   |  R2   |
   +---------------+-------+-------+

In this diagram, R1 is the Destination GPR and R2 is the Source GPR. All 16 GPRs may participate in either position in an RR- format instruction.

RX - Register-to-indeXed-storage

The RX mode is used where it is necessary to transfer data to or from main memory. RX instructions occupy a fullword and must begin on even addresses. They have the following format:

   |0             7|8    11|12   15|16                            31|
   +---------------+-------+-------+--------------------------------+
   |    OP-Code    |  R1   |  X2   |              A                 |
   +---------------+-------+-------+--------------------------------+

As in the RR format instructions, the R1 field specifies the GPR that is to participate in the data transfer. The X2 register specified one of 15 GPRs which is to act as an index register, which along with the value "A" will form a memory address which will participate in the data transaction.

The effective address is formed by algebraically adding the contents of the GPR specified by the X2 field to the unsigned value of "A". This effective address, "E", is used to access memory to perform the desired function.

Only 15 of the 16 GPRs may be used as index registers. GPR 0 may not participate in indexing as the zero value means that no indxing is to take place.

RS - Register-to-Storage

The RS format is superficially similar to the RX format except that memory is not subsequently accessed; the calculated effective address is taken as the data to be acted upon. This is commonly known as "immediate mode". The format for an RS instruction is:

   |0             7|8    11|12   15|16                            31|
   +---------------+-------+-------+--------------------------------+
   |    OP-Code    |  R1   |  X2   |              A                 |
   +---------------+-------+-------+--------------------------------+

As in the RX format, only 15 of the GPRs may participate in the X2 field, as a zero value specifies no indexing is to take place.

A special form of the RR and RX formats exists for the Branch instructions and takes the form:

   |0             7|8    11|12   15|
   +---------------+-------+-------+
   |    OP-Code    |  M1   |  X2   |
   +---------------+-------+-------+

and

   |0             7|8    11|12   15|16                            31|
   +---------------+-------+-------+--------------------------------+
   |    OP-Code    |  M1   |  X2   |              A                 |
   +---------------+-------+-------+--------------------------------+

Note that the R1 field is replaced by the M1 designator which is used to store a mask to be compared to the PSW for conditional jumps. This will be treated later.

The Processor Status Word

The thirty- two bit Processor Status Word (PSW) in the Interdata machines is used to store the current context of the machine. This encompasses the current location (Program Counter, or PC), the current Condition Codes (CC), and the current machine status. This status word may be manipulated by the program directly, or may change as a by- product of instruction execution or machine status changes (e.g. interrupts).

The PSW appears thusly:

   |0                    11|12   15|16                            31|
   +-----------------------+-------+--------------------------------+
   |    Machine Status     |  CC   |     Current Program Counter    |
   +-----------------------+-------+--------------------------------+

The Machine Status bits are as follows:

     PSW Bit      Function
   ----------   ------------

       0          Wait
       1          Interrupt Enabled
       2          Machine Malfunction Interrupt Enabled
       3          Fixed-Point Divide Fault Interrupt Enabled
       4          Reserved
       5          Floating-point Divide Fault Interrupt Enabled
     6 - 11       Unassigned

The functions are, in turn:

Wait: In the wait state, the processor is in a high- speed, interuptable loop. No processing is performed whilst in this state, and if interrupts are disabled, this state is equivalent to a halt.
External Interrupt Enabled: The presence of this bit indicates that external devices are allowed to interrupt the normal processing flow of the machine. Interrupting technique will be covered later.
Machine Malfunction Interrupt Enabled: On machines equipped with the optional mainstore parity generation/ dection circuitry, this bit allows the parity logic to signal that a corrupt memory location has been accessed.
Fixed-Point Divide Fault Interrupt Enabled: On machines with the optional hardware (microcode, actually) multiply/ divide feature, this bit allows the processor to interrupt itself if a divide fault occurs in a fixed- point calculation. This is usually a divide- by- zero fault.
Floating-point Divide Fault Interrupt Enabled: This is the same as above, but for floating- point hardware.

Condition Codes in the PSW

There are four condition code bits defined by the Interdata architecture - C, V, G, and L, and occupy, sequentially, bits 12 through 15 in the PSW. These function thusly:

C - Carry/Borrow: This bit is set when an arithemetic operation causes a carry out of a halfword, or a borrow on a subtraction. This bit is also used in I/O testing to indicate the status of a device's Busy (BSY) bit.
V - Overflow: An overflow is deemed to occur when an arithmetic operation has produced a result that cannot be contained within the data size selected plus the carry bit (e.g. two positive numbers being added that produce a negative result). In I/O testing, this reflects a device's Examine Status (EX) bit.
G - Greater than zero: This bit gets set if the result of a calculation is greater than zero. In I/O use, this bit reflects the "End of Medium" (EOM) status.
L - Less than zero: This bit gets set following transfers or arithmetic operations if the result is less than zero. For I/O, reflects Device Unavailable (DU) status.

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Last Modified: Sat May 13 13:21:28 EDT 2000