PDP-12 User's Manual




The PDP-12 Programmed Data Processor is a versatile digital computer which includes within its single central processor two distinct operating modes, each with its own complete instruction set. This versatility of the PDP-12 makes it, on the one hand, a laboratory-oriented machine with several built-in facilities for input/output, auxiliary storage, and control and sensing of external equipment, and, on the other hand, a general-purpose computer with a flexible input/output capability to which numerous peripheral devices may be easily attached. The central processor logic is fully parallel using a basic word length of 12 bits. The instruction cycle time is 1.6 microseconds; most instructions require from 1 to 3 cycles for execution.

Like its predecessor, the LINC-8, the PDP-12 operates in one mode as a LINC (Laboratory INstrument Computer), and in the other mode as a PDP-8 computer - specifically, a PDP-8/I. Unlike the LINC-8, however, the PDP-12 has one central processor and both operating modes have equal status. (In the LINC-8, the LINC mode was subordinate to the PDP-8 mode). The computer may be stopped and started in either mode, and programs may switch from one to the other at will. Computations in one mode are immediately available to programs operating in the other mode because only one set of processing registers is involved.

The PDP-l2 is offered in three configurations: A, B, and C in order of decreasing capacity. The two smaller systems, B and C, are expandable into the A configuration. The system discussed in this handbook is the PDP-12A.

The basic memory capacity of the PDP-12 is 4096 (4K) 12-bit words and can be expanded to 32,768 (32K) words of core storage.

[GIF Image of PDP-12 Block Diagram]

Figure 1-1. PDP-12 Programmed Data Processor System, Functional Block Diagram

As shown in Figure 1-1, the input/output facilities are available to the two operating modes of the PDP-12 in the following manner through LINC mode programming:

In addition to these, the PDP-12 is also equipped with a positive logic PDP-8/I type input/output (I/O) bus, to which can be attached, all 8 family peripherals and options such as a high- speed paper tape reader and punch, as well as the standard ASR-33 Teletype.

Central Processor

The central processor contains all the logic and registers required to carry out the functions of both operating modes of the PDP-12. The central processor can best be described in terms of its active registers:

Accumulator (AC) 12 Bits -
This register contains data being operated upon. Its contents may be shifted or rotated right or left; incremented, cleared, or complemented; stored in memory or added to the contents of a memory register; and logically or arithmetically compared with the contents of any memory register. The AC holds the sum after an addition, and part of the product after a multiplication. The AC is also involved in the transfer of data to and from various other registers outside the central processor.

Link (L) 1 Bit -
The Link is an extension of the AC. When a carry occurs out of bit 0 of the AC during a 2's complement addition, the Link is complemented. It may be set or cleared independently of the AC, and may be included (or not) in shifting and rotating operations performed on the contents of the AC.

Multiplier Quotient (MQ) 12 Bits -
This register is used as a second arithmetic register for multiply and some rotate instructions. It is also used for the extended Arithmetic Option (KE12) functions.

Program Counter (PC) 12 Bits -
This register contains the address of the next instruction to be executed within the memory field selected by the Instruction Field Register (see below). In PDP-8 mode, the PC acts as a 12-bit counter; in LINC mode, it acts as a 10-bit counter.

Memory Address Register (MA) 12 Bits -
This register contains the address for memory references. Whenever a core memory location is being accessed, either for reading or for writing, the MA contains the address of that location.

Instruction Register (IR) 12 Bits -
This register contains the complete binary code of the instruction being executed.

Memory Buffer (MB) 12 Bits -
All information passing between memory and any other register in the PDP-l2 must go through the Memory Buffer Register, whether the transfer involves the central processor, an external device, or another memory register.

Instruction Field Register (IF) 5 Bits -
This register selects the memory field containing the executable program. In LINC mode, it is used to designate one of up to thirty-two 1024- word segments. In PDP-8 mode, the three high- order bits of the IF are used to designate one of up to eight 4096- word fields.

Data Field Register (DF) 5 Bits -
This register selects the memory field containing data to be indirectly accessed by the memory reference instructions of a program. The fields are specified in each mode in the same way that the IF specifies the instruction Field.


The principal unit of core memory is a module of 4096 (4K) 12-bit words. Additional 4K banks may be added, to a total of eight, or 32,768 words. Within each bank, the logical organization of memory depends on the operating mode. In LINC mode, the bank is divided into four 1024-word segments. At any given time, only two of these segments are active: the Instruction Field, which contains the executable program and the directly accessed data; and the Data Field, which contains only indirectly accessed data. Absolute addresses may be assigned and changed at will using the IF and DF described above.

In the PDP-8 mode, the memory field, which is the size of a 4K module, is divided into 32 pages of 128 words each. Within a single page, data may be accessed directly; between pages, indirect addressing must be used. If more than 4K of memory is provided, the IF and DF registers specify the active fields.

Operating Modes

The two operating modes, LINC and PDP-8, are independent of each other, though they may be combined and intermixed within a program. The user can run programs from the already-existing libraries for the 8 family of computers including the LINC-8. Using the I/O Handler (PROGOFOP simulator) program provided with the PDP-12 basic software, most programs written for the LINC-8 can be run without modification. (Some LINC-8 programs may require slight changes). A complete software system designed for the PDP-12 allows the programmer to assemble coding for either or both modes in a single program.


In this mode, the instruction set of the classic LINC computer is implemented. In addition, several new provisions are available:

Extended Tape Addressing - This allows the programmer to transfer information between LINCtape and any section of core, removing the restriction to specific quarters of a given memory field. Other features include:

  1. Tape interrupt - which connects the tape processor status to the Program Interrupt.
  2. No-pause - which permits the central processor to resume operation after initiating a tape transfer without waiting for completion.
  3. Hold-motion - which allows a unit to remain in motion after deselection.

I/O Bus Access - In LINC mode the user has immediate access to those devices activated by LINC instructions A-D, DISPLAY, RELAYS, SENSE LINES, and TAPE. Any other device connected to the I/O bus may be directly accessed from LINC mode programming by means of a special two-word instruction, in which the second word enables the bus and initiates the PDP-8 IOT timing chain. This second word is interpreted as a standard PDP-8 IOT instruction. The program continues to operate in LINC mode.

Special Functions - The LINC programmer may, by setting certain flip-flops: 1) change the size of characters displayed on the CRT; 2) enable the program trap, which intercepts certain LINC instruction codes; 3) disable interrupts from the ASR-33; 4) speed the sampling of analog inputs; and 5) clear the PDP-12 status by generating an I/O preset pulse.

PDP-8 Mode

In this mode, the user has available the entire PDP-8/I instruction set.

Interaction Between Modes

The user may switch from one mode to the other at will. In LINC mode, execution of the instruction PDP causes the processor to change immediately to PDP-8 mode operation, and all subsequent instructions are interpreted as PDP-8/I instructions. To switch from PDP-8 mode to LINC mode the IOT instruction LINC is used.

Input/Output Facilities and Display

As can be seen from Figure 1-1, there are two main paths for the transmission of data from the central processor or memory to peripheral devices. One path, which is controlled by LINC mode programming, leads to the CRT display, LINCtape, A-D converter, and relays. The other path, which is the I/O bus, leads to the ASR-33 and to a large number of optional devices, such as: plotters, high-speed tape and card readers, disk storage, line printers, etc.


The Cathode Ray Tube Display has a 58.5-square inch (6.5 x 9 inches) screen, on which individual points and whole characters may be displayed. The unit has two intensification channels, controlled by programming and by a switch on the display. Characters are plotted on a 4 point x 6 point matrix; a full character can be displayed with two instructions. Provision is made for displaying two sizes of characters.

Data Terminal

The data terminal provides a flexible means of receiving analog inputs and controlling the operation of external equipment not directly interfaced to the PDP-12.

Analog Inputs - Sixteen analog inputs feed a 10-bit A-D converter. A single LINC mode installation samples any of the 16 channels. A second set of sixteen inputs with preamplifiers, can be added to the basic facility.

Eight of the inputs, taken from phone jacks mounted on the Data Terminal Panel, are fed through preamplifiers to the converter. The remaining eight are taken from continuously-variable , ten-turn potentiometers, which are also mounted on the panel.

Relay Buffer - Six relays, mounted on the Data Terminal Panel, may be switched by means of a LINC mode instruction. The relays may be used to start and stop operations in external equipment. The status of the relays can be read back into the AC.

Auxiliary Scope Connector - A Blue Ribbon connector mounted on the Data Terminal Panel is wired to accept an auxiliary CRT for displaying information also sent to the screen of the built-in scope.

Sense Lines

These 12 digital sense lines may be individually tested with a LINC mode instruction.


Two TU55 transports are controlled by a fully-buffered tape processor; once initiated by the LINC program, tape operations are carried out independently of the central processor. Tapes normally are written and read in standard LINCtape format, though non-standard format can be used. A special hardware option, TC12-8, permits the use of PDP-8 DECtape format. In addition to the basic LINCtape commands, the PDP-12 also includes an Extended Operations facility, which allows, among other features, the transmission of data between tape and any program-defined area of memory, and the addition of TU55 transports to a total of eight.

Input/Output (I/O) Bus

This connecting facility provides the control and data transmission path between the central processor and any peripheral devices that are attached to the bus. For some devices, such as: paper tape readers and punches, line printers, and incremental plotters, data is transferred via the accumulator (AC). Others, including magnetic tape and disk, use the three-cycle or single-cycle Data Break for direct memory access. The I/O bus uses positive logic and accepts peripherals used with 8 family of computers. The processor is prewired to accept the following I/O bus options:

Many other devices can be added to the PDP-12 I/O bus with the inclusion of the BA12 Peripheral Expander and the DW08 I/O and Bus Converter. The Peripheral Expander allows the addition of high- speed paper tape reader and punch, card reader, and optional communication interfaces. The Bus Converter provides for the addition of disk and IBM-compatible magnetic tape storage, and A/D and D/A converters and associated multiplexers designed for the negative-logic PDP-8 I/O Bus.

Keyboard/Printer (ASR-33)

An important means of direct communication between the user and the operating program is the ASR-33 Keyboard/Printer, standard on all configurations of the PDP-12. The ASR-33 is connected to the I/O bus, and can be accessed for input or output by programs in either operating mode. The ASR-33 is equipped with paper tape reader and punch; the reader and keyboard use the same input path and instructions, while the printer and punch use the same output path and instructions. The maximum transfer rate in either direction is 10 characters per second.

The ASR-33 has both full- and half- duplex capability. In full- duplex operation, data may be transmitted in both directions simultaneously, without interference. In half-duplex operation, data may be transmitted in only one direction at a time.


The following symbols and abbreviations are used throughout this handbook:

[Transcribers's note: I've used a C-like syntax for subscripts and bit- ranges. Subscripts, such as base- denotions are described with "(" and ")" characters. Bit- ranges are described with x:y with "x" as the first bit in the range and "y" as the last delimited by "[" and "]" characters. Boolean "NOT"s are prefixed with a "!" rather than denoted by a bar over the term. A forward arrow is styled "->".]

AC, MB, PC, MQ, MA, L, IF, DF, IR -
Central Processor registers: Accumulator, Memory Buffer, Program Counter, Multiplier- quotient. Memory Address, Link, Instruction Field, Data Field, Instruction Register, respectively.

R -
General representation of any register.

C(R) -
The contents of register R.

C(R[j]) -
The contents of bit j of register R.

C(R[j:k]) -
The contents of bits j through k, inclusive, of register R.

C(RL) -
The contents of the left half of register R.

C(RR) -
The contents of the right half of register R.

!C(R) -
The complement of the contents of register R.

Y -
The effective address of an operand.

I -
The indirect address bit of an instruction. In LINC mode, I represents bit 7: in PDP-8 mode, bit 3.

C(R) -> C(S) -
The contents of register R replace those of register S.

N -> C(R) -
The quantity N replaces the contents of register R.