PDP-12 User's Manual



Almost every program, at some time during its execution, will need an item of data stored in memory. Such an operand can be obtained only by specifying: the address of the register in which it is stored (or to be stored, if the data is going the other way). An instruction which requires a reference to memory can designate the desired location in two ways. It may include the address or the operand as part of the instruction itself and directly address the location of the operand. Or, the instruction may specify the address, not of the operand, but of a register containing the address of the operand, thus indirectly addressing the data storage register.

The need for indirect addressing is readily apparent: with eleven bits required to specify a Data Field address, not much is left of a 12-bit word to use for instruction codes. It is necessary to reduce the number of address bits available within a memory reference instruction, and to use a limited set of directly addressable locations as pointers containing the effective addresses of the desired data. The LINC instruction set provides for both types of addressing.


In LINC programming, direct access to memory registers is limited to the Instruction Field. A full address in this field requires ten bits (0000-1777), leaving only two bits for instruction codes. The three instructions, ADD, STC, and JMP, are described in detail in Section III. The format of a direct-address instruction is shown in Figure 3-2. Bits 0 and 1 are used for the operation code, bits 2-11 for the address.

       /Code\  /-------------- Address ----------------\
      /      \/                                         \
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |

Figure 3-2. Direct Address Instruction Format


For access to registers in the Data Field. an indirect address is required. The instruction specifier one of a small set of special registers which are used to hold the effective address of desired data. The format of these B-class instructions is shown in Figure 3-3. Bits 3-6, are available for operation codes: bits 8-11, together with bit 7, determine which of four addressing schemes is to be used.

       /- 0 -\     /  Operation \      /----- B ------\
      /       \   /     Code     \    /                \
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
              \   /               \   /
               -1-                 -I-

Figure 3-3. B-Class Instruction Format


In a B-class instruction, the contents of bits 8-11, when not zero, designate one of fifteen registers at locations 0001-0017 of the Instruction Field. The contents of the specified B-register are used to determine the effective address of the operand. When the contents of bits 8-11 are zero, the effective address is found in the register which immediately follows the referencing instruction.

Bit 7, the I-Bit. determines the manner in which the register designated by bits 8-11 is to be used in locating the operand. There are four addressing schemes, described in the following table:

Bit 7(I) = 0; Bits 8-11(B) = 00 -
The effective address is the contents of bits 1-11 of the register immediately following the instruction. [aka "absolute mode"]

Bit 7(I) = 1; Bits 8-11(B) = 00 -
The effective address is the address of the register immediately following the instruction. The operand itself is in this register. [aka "immediate mode"]

Bit 7(I) = 0; Bits 8-11(B) = 01-17 -
The effective address is the contents of bits 1-11 of the designated B-register.

Bit 7(I) = 1; Bits 8-11(B) = 01-17 -
The effective address is the contents, incremented by 1, of bits 1-11 of the designated B-register. Ten-bit indexing is used.

In the first scheme, the register which follows the referencing instruction contains the effective address. In the second scheme, the operand itself is in that register.

When either of these two schemes is used, that is, when the contents of bits 8-11 are zero, the program counter automatically skips over the register immediately following the instruction, and the next instruction is fetched from the second register following.

The following examples illustrate the use of all four addressing schemes.

The instruction STA (Store Accumulator) causes the contents of the AC to be stored in memory. The operation code for STA is 1040. The register R is the one which immediately follows that containing the STA instruction.

(1) STA 0       Octal Code:  1040          C(R)=2345
                Destination of C(AC):      Location 2345

(2) STA I 0     Octal Code:  1060
                Destination of C(AC):      Location R

(3) STA 12      Octal Code:  1052          C(0012)=3456
                Destination of C(AC):      Location 3456

(4) STA I 12    Octal Code:  1071          C(0012)3456
                Destination of C(AC):      Location 3457
                                           (The contents of B-register 0012
                                           are incremented by 1, and the
                                           result, 3457 is used as the
                                           effective address.)
In the next example, the use of these addressing schemes in a program sequence is demonstrated. The instruction ADA (Add to Accumulator) adds the operand to the contents of the AC, leaving the result in the AC. The program sequence starting at location 1000 adds the numbers N(1), N(2), N(3), and N(4), leaving the sum in the AC.

Field                      Octal
Address     Contents       Code                   Remarks

0007         1500                    Replaced by 1501 after indexing

1000         ADA           1100      Indirect through 1001. Adds N(1) to C(AC)
1001         1477                    Address of N(1)
1002         ADA I         1120      Direct to 1003; adds N(2) to C(AC)
1003         N(2)
1004         ADA 7         1107      Indirect through 7 to 1500.  Adds N(3)
1005         ADA I 7       1127      Indirect through 7, indexed.  Adds N(4)
1477         N(1)                    These registers may be anywhere
1500         N(3)                    in the instruction or Data
1501         N(4)                    fields.
B-Register Indexing

When the B-indexing scheme is used (I = 1, B != 00), effective addresses may specify registers in either memory field, but the B-register cannot be incremented from one field to the other. Indexing is only over ten bits, as it is in the PC; the two high-order bits are unaffected. Thus, the contents of the B-register will be incremented from 1777 to 0000, from 3777 to 2000, from 5777 to 4000, and from 7777 to 0000. To change access from one field to the other, it is necessary to change the contents of bit 1 of the B-register.

Bit 0 of the B-register has no effect in most indirect references. but it does have a special use in half-word operations, in multiplication, and in character display.


Three LINC mode instructions - SET, XSK, and DIS - have specialized memory reference schemes. Although each of them access memory in a unique way, all make use of one of the registers in locations 0000 through 0017. These are called a-registers, to differentiate between these instructions and those of the B-class.

SET and XSK are described in Section III. DIS is described in Section IV.