PDP-12 User's Manual

CHAPTER 3
LINC MODE PROGRAMMING

Section III. LINC MODE INSTRUCTIONS

INSTRUCTION FORMATS

There are three basic LINC mode instruction formats, to wit:

(1) Direct Address (Figure 3-2)

     Operation
       /Code\  /-------------- Address ----------------\
      /      \/                                         \
      +---+---+---+---+---+---+---+---+---+---+----+----+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
      +---+---+---+---+---+---+---+---+---+---+----+----+

This class consists of the three instructions ADD, STC, and JMP.

(2) Indirect Address, B-class (Figure 3-4)

       /- 0 -\     /  Operation \      /----- B ------\
      /       \   /     Code     \    /                \
      +---+---+---+---+---+---+---+---+---+---+----+----+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
      +---+---+---+---+---+---+---+---+---+---+----+----+
              \   /               \   /
               -1-                 -I-

Figure 3-4. B-Class Format

This class consists of 16 B-class instructions, with operation codes between 1000 and 1740.

(3) a-class and others (Figure 3-5)


       /All Zeros\                  I
      /           \               /   \
      +---+---+---+---+---+---+---+---+---+---+----+----+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
      +---+---+---+---+---+---+---+---+---+---+----+----+
                  \               /   \                 /
                   \  Operation  /     \   Operation   /
                        Code            Code, a-register
                                    or function designators

Figure 3-5. a-Class and Non Memory Reference Format

There are 16 basic instructions and instruction subclasses with this format, giving a total of 43 instructions with operation codes between 0000 and 0740. The I-bit has various functions depending on the subclass.

INSTRUCTION DESCRIPTIONS

The descriptions are organized according to function and class, as follows:

Full-word Data Transfers -
STC, LDA, STA

Full-word Arithmetic -
ADD, ADA, ADM, LAM, MUL

Full-word logic -
BCL, BSE, BCO

Full-word comparison -
SAE, SRO

Half-word operations -
LDH, STH, SHD

a-class operations -
SET, XSK

Program control -
JMP

Shift and rotate -
ROL, ROR, SCR

Skips -
APO, AZE, LZH, QLZ, FLO, SNS, SXL, KST

Miscellaneous -
HLT, CLR. COM, NOP, QAC

Console Switches -
LSW, RSW

Mode control switch -
PDP

I/O Bus Enable -
IOB

Memory address control -
LIF, LDF, IOB/IOTs

Program interrupt -
IOB/IOT, DJR

Special Functions -
ESF, SFA

Instructions related to the Display, Data Terminal, and LINCtape are described in Sections IV, V, and VI.

In general, the description of each instruction is presented in the following manner:

Mnemonic - Operation Performed
Form
Octal code
Execution time
Operation

The second line shows the general form of the instruction when used in a program. The octal code is that of the instruction itself, plus the octal value of any other elements which may be present, such as the I-bit or B-register bits. (The I-bit, for example, being represented by bit 7, has an octal value of 20 when it is present).

FULL-WORD DATA TRANSFERS

These three instructions move complete 12-bit words between the Accumulator and Memory.

STC - Store and Clear

Form: STC Y
Octal code: 4000 + Y
Execution time: 3.2 microseconds
Operation: Store the contents of the AC in register Y, then clear the AC. This is a direct address instruction; Y must be in the instruction Field.

LDA - Load Accumulator

Form: LDA I B
Octal code: 1000 + 20I + B
Exectution time: 4.8 microseconds; 3.2 µsec. when I=1 and B=00
Operation: Place the contents of register Y, where Y is the address specified by I and C(B), in the AC. The previous C(AC) are lost; the contents of Y are unchanged.

STA - Store Accumulator

Form: STA I B
Octal code: 1040 + 20I + B
Execution time: 4.8 microseconds; 3.2 µsec. when I=1 and B=00
Operation: Store the contents of the AC in memory register Y, where Y is the address specified by I and C(B) The previous C(Y) are lost; the contents of the AC are not changed.

FULL-WORD ARITHMETIC

The instructions ADD, ADA, and ADM use 1's-complement arithmetic. If, as the result of an addition, a 1 is carried out of bit 0 of the sum, 1 is added to the sum. This end-around carry is the defining property of a 1's-complement addition. If there is no carry, the sum is left as is.

Example 1:
            2435
           +1704
           -----
            4341      no carry; sum is left as is.

Example 2:
            2435
           +5704
           -----
       +- 1 0341
       +--->   1       end-around carry; 1 added to sum.
           -----
            0342

In either case, the Link is not affected.

The instruction LAM uses 2's-complement arithmetic. If a carry from bit 0 of the sum occurs, the Link is set to 1; the sum is left unaffected.

Overflow

In any LINC mode addition, a number is considered to be positive if its high-order bit (bit 0) is 0, and negative if this sign bit is 1. Whenever two addends of like sign produce a sum of opposite sign, overflow is said to occur. When this happens, the overflow flip-flop, FLO FF, is set to 1. If no overflow occurs, FLO FF is set to 0. Overflow cannot, by definition, occur when the addends have unlike signs. Note that overflow and carry are not the same thing.

INSTRUCTIONS

ADD - Add to Accumulator (Direct Address)

Form: ADD Y
Octal code: 2000 + Y
Execution time: 3.21 µsec
Operation: The contents of register Y are added to the contents of the AC using 1's-complement addition, leaving the sum in the AC. The previous C(AC) are lost; the Link and C(Y) are not changed.

ADA - Add to Accumulator (B-Class)

Form: ADA I B
Octal code: 1100 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: The contents of register Y, as specified by I and C(B), are added to the contents of the AC using 1's-complement addition, leaving the sum in the AC. The previous C(AC) are lost; the Link and C(Y) are not changed.

ADM - Add to Memory

Form: ADM I B
Octal Code: 1140 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: The contents of register Y, as specified by I and C(B), are added to the contents of the AC using 1's-complement addition, leaving the sum in both the AC and Y. The previous contents of both registers are lost; the Link is not changed.

LAM - Link Add to Memory

Form: LAM I B
Octal code: 1200 + 20I + 8
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00

NOTE

The description of the operation, below, presents the logical sequence of events; in practice, the operations are carried out simultaneously.

Operation: The contents of the Link are added to the contents of the AC using 2's complement addition, leaving the sum in the AC. If there is a carry out of bit 0, the Link is set to 1; if not, the Link is cleared. Next the contents of register Y, as specified by I and C(B), are added to the new contents of the AC, again using 2's-complement addition: the sum is left in both the AC and Y. If there is a carry from bit 0 this time, the Link is set to 1; if not, the Link is left unchanged.

Example: C(AC) = 3743, C(Y) = 6517, C(L) = 1.

(1)    C(AC)         3743
       +C(L)        +   1
                    -----
                     3744        no carry; Link is cleared.

(2)    C(AC)        3744
       +C(Y)       +6517
                   ----- 
                    2461         carry; Link is set to 1.
Results: C(AC) = 2463, C(Y) = 2463, C(L) = 1

MUL - Multiply

Form: MUL I B
Octal code: 1240 + 20I+ B
Execution time: 9.6 microseconds; 8 µsec. when I=1 and B=00
Operation: The contents of the AC (multiplicand) are multiplied by the contents of register Y (multiplier). The product is left in the AC and the MQ. The sign of the product appears in the Link, and AC[1:11], and the absolute value of the low- order bits appear in MQ[0:10]. The sign appears in AC[0] and the Link. The contents of the MQ can be accessed by using the QAC instruction.

The multiplier and multiplicand are treated as 12-bit 1's-complement numbers. If bit 0 of an operand is set to 1, the operand is negative. The sign of the product is always correct, that is, operands of like sign give a positive product, and operands of unlike sign give a negative product. Overflow cannot occur: the Overflow flip-flop is not affected by multiplication.

Either integer or fractional operands may be specified, as follows: if bit 0 of the designated B-register contains a 0, the operands are treated as integers; the binary points of both multiplier and multiplicand are considered to be to the right of bit 11. If C(B[0]) = 1, the operands are taken as fractions; the binary points are considered to be between bit 0 (sign) and bit 1. Note that when I = 1 and B = 00, there is no effective address. In this case, integer multiplication is performed.

When integer multiplication is performed, the low-order 11 bits of the product appear in bits 1-11 of the AC and the absolute value of the low order 11 bits of the product appear in bits 0-10 of the MQ. The sign appears in AC[0] and the Link. The high-order bits of the product are lost.

When fractional multiplication is performed, the high-order 11 bits of the product appear in AC[1:11], and the absolute value of the low-order bits appear in bits MQ[0:10]. The sign appears in AC[0], and the Link. The contents of the MQ can be accessed by using the QAC instruction.

Examples: (all octal form)

(a) Integers


   1.
                0432      C(AC)
               x0006      C(Y)
               -----
            00003234     product     C(AC)=3234 C(MQ)=6470

   2.
                2764
               x0153
               -----
            00476374     C(AC)=2374  C(MQ)=4770

   3.
                2764
               x7624     (=-153)
               -----
            77301403     (=-00476374) C(AC)=5403 (=-3154) C(MQ)=4770

(b) Fractions


   1.
                0432   C(AC)
               x0006   C(Y)
               -----
            00003234   product  C(AC)=0000 C(MQ)=6470

   2.
                2764   C(AC)
               x0153   C(Y)
               -----
            00476374   product C(AC)=0117  C(MQ)=4770

   3.
                2764   C(AC)
               x7624   C(Y)
               -----
            77301403   (-00476374)  C(AC)=7660  C(MQ)=4770

FULL-WORD LOGIC

In each of these Boolean functions, the operation is performed between corresponding bits of the AC and the operand, independent of the other bits in either word.

BCL - Bit Clear

Form: BCL I B
Octal code: 1540 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: For each bit of the operand that is a 1, the corresponding bit of the AC is cleared to 0. For each operand bit that is a 0, the corresponding AC bit is unchanged. The operand is not changed. The following truth table gives the relationship between the corresponding bits, with the results of the comparison.

            C(AC[j])

             0   1
           +--------
         0 | 0   1
C(Y[j])    |
         1 | 0   0

The Boolean statement of this relation is AC V !Y
Example:
        C(AC)=2307          010011000111
        C(Y) =1616          001110001110
        ----------          ------------
     Result: =2101          010001000001
BSE - Bit Set

Form: BSE I B
Octal code: 1600 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: For each bit of the operand that is a 1, the corresponding bit of the AC is set to 1. For each operand bit that is 0, the corresponding AC bit is not changed. The operand is not affected. The truth table for this relation, which is the familiar inclusive OR is given below:

            C(AC[j])

             0   1
           +--------
         0 | 0   1
C(Y[j])    |
         1 | 1   1

The Boolean statement of this relation is AC V Y.
Example:
       C(AC)= 2307            010011000111
        C(Y)= 1616            001110001110
       -----------            ------------
     Result: =3717            011111001111
BCO - Bit Complement

Form: BCO I B
Octal code: 1640 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: For each bit of the operand that is a 1,the corresponding bit of the AC is complemented. For each operand bit that is 0, the corresponding AC bit is unchanged. The operand is not changed. The truth table for this relation, which is the exclusive OR, is given below:

            C(AC[j])

             0   1
           +--------
         0 | 0   1
C(Y[j])    |
         1 | 1   0

The Boolean statement of this relation is AC V [The actual symbol is a "V" struck through with a "-"] Y
Example:
        C(AC)= 2307     010011000111
         C(Y) =1616     001110001110
        -----------     ------------
      Result: =3511     011101001001
FULL-WORD COMPARISON

In both of these operations, the next succeeding instruction in the program sequence is skipped if the stated condition is met. When B != 00, this presents no unusual circumstance. When B=00, however, the register immediately following the skip instruction contains either the operand itself or its address. When such is the case, this register is automatically passed over, and the one beyond that is considered to be the next register in the program sequence. If a skip occurs under these conditions, the program will proceed from the third register following the skip instruction.

SAE - Skip If Accumulator Equal (To Operand)

Form: SAE I B
Octal code: 1440 + 20I + B
Execution time: 4.8 µsec; 3.2 µsec when I=1 and B=00
Operation: If the contents of the Accumulator are equal to the contents of Y (where Y is specified by I and B), the next instruction in the program sequence is skipped. Otherwise, the program continues without skipping. The contents of the AC and of Y are not changed.

SRO - Skip and Rotate

Form: SRO I B
Execution time: 4.8 µsec.; 3.2 µsec. when I=1 and B=00
Operation: If bit 11 of the operand is 0, the next instruction in the program sequence is skipped; otherwise, the program proceeds without skipping. After the bit is tested, the contents of Y (that is, the operand) are rotated right one place.

Example:

 Address      Contents                  Action

   p          SRO I O        /The operand is in register p + 1.
   p+l        3725           /Operand. C(R[11])= 1, so no skip.
   p+2        ....           /Program continues from here.
   p+3
After the test is performed, the contents of p+1 are rotated right one place; the result, which is retained in p+1, is 5752. If the instruction in register p were now to be executed again, the skip would occur, because the new contents of bit 11 of p+1 equal 0. The program would then proceed from register p+3, skipping the instruction in p+2.

HALF-WORD OPERATIONS

Half-Word Addressing

The three instructions, LDH, STH, and SHD, operate on either half of a memory register, independent of the other half. The addressing scheme is basically that of other B-class instructions, with the following difference: Whenever bit 0 of the register containing the effective address holds a 0, the left half of the addressed operand is used; when bit 0 contains a 1, the right half is used. In either case, the data are transferred or compared between the designated half of the operand and the right half of the Accumulator.

The following examples demonstrate the effects of half-word addressing. The instruction LDH transfers the designated half of the operand into the right half of the AC; the left half of the AC is cleared.

1. LDH 0: I = 0, B = 00. C(R) = 0370 (R is the register following LDH). The effective address is 0370. Because C(R[0]) = 0, the contents of the left half of register 0370 are placed in the right half of the AC.

2. LDH 12: I = 0, B = 12. C(0012) = 4370. Bit 0 of B-register 12 contains a 1; therefore, the contents of the right half of register 0370 are placed in the right half of the AC.

3. LDH I 0; I = 1, B = 00. C(R) = 6527. This is a direct reference, so that there is no explicit effective address. In this case, the left half of the operand in register R is taken. In the example, the quantity 65 is placed in the right half of the AC.

4. LDH I 12; I = 1, B = 12. C(0012)= 0370. The effective address, that is, C(0012), must be incremented before it is used. Instead of 1, however, 4000 is added to the contents of the B-register (remember that the half- word indicator is in bit 0). Given the conditions specified above, the contents of B-register 12 are first augmented from 0370 to 4370, and the right half of the operand in register 0370 is taken. If a second LDH I 12 is now executed, the B-register is again incremented by 4000. The sum which leaves C(B[0] )=0, results in a carry out of the high-order bit. The carry causes 1 to be added to the sum, resulting in a final effective address of 0371. The new operand, then, is taken from the left half of the new register. The indexing sequence is thus: left half, right half, left half of the next succeeding register, etc.

Because the basic indexing scheme is operative only over bits 2-11 of the B-register, half- word addressing proceeds from the right half of register 1777 to the left half of register 0000, and from the right half of register 3777 to the left half of register 2000. C(B) are thus incremented from 1777 to 5777 to 0000, and from 3777 to 7777 to 2000.

NOTE

Another way of looking at the half-word indicator may help clarify this method of addressing. If the indicator is considered to be just to the right of bit 11, rather than in bit 0, it becomes apparent that half- word indexing is just like full- word indexing, with 1 added to the low-order bit, that is, the half- word indicator, each time. You can, if you like, imagine a binary point between the half-word indicator and bit 11 of the B-register, so that successive addresses might be read as 0370, 0370½, 0371, 0371½, 0372, etc. (Or, in octal, 0370.0, 0370.4, 0371.0, 0371.4, 0372, etc.).

LDH - Load Half

Form: LDH I B
Octal code: 1300 + 20I + B
Execution time: 4.8 µsec.; 3.2 µsec. when I=1 and B=00
Operation: The contents of the designated half of register Y (where Y is specified by I and C(P) are placed in the right half of the Accumulator. The left half of the AC is cleared. The previous C(AC[r]) are Lost. The contents of Y are not changed.

STH - Store Half

Form: STH I B
Octal code: 1340 + 20I + B
Execution time: 4.8 µsec.; 3.2 µsec. when I=1 and B=00
Operation: The contents of the right half of the Accumulator are stored in the designated half of register Y. The contents of the AC and of the other half of Y are not disturbed.

SHD - Skip If Half Differs

Form: SHD I B
Octal code: 1400 + 20I + B
Execution time: 4.8 µsec.; 3.2 µsec. when I=1 and B=00
Operation: If the contents of the designated half of register Y are not equal to the contents of the right half of the AC, the next instruction in the program sequence is skipped; otherwise, the program proceeds without skipping. The contents of Y and of the AC are not changed. As in the other B-class skips (SAE, SRO), the register immediately following the SHD is automatically passed over when B=00.

a-CLASS OPERATION

Each of these instructions uses the registers 0000-0017 in a unique way. A third a-class instruction, DIS, is described in Section IV, CRT Display.

SET - Set a-Register

Form: SET I a
Octal code: 0040 + 20I + a
Execution time: 6.4 µsec.; 4.8 µcsec. when I=1
Operation: The contents of the a-register specified by bits 8-11 of the SET instruction are replaced by the operand, whose location is determined by the state of the I-bit, as follows:

If I = 1, the operand is in the register immediately following that containing the SET instruction.

If I = 0, the effective address of the operand is in the register immediately following that containing the SET instruction.

SET always requires two successive locations; the program always continues from the second register following, as in this example:

Address    Contents                   Action

p          SET I 15         /THE OPERAND IS IN REGISTER p+l
p+l        2537             /OPERAND. 2537 1S STORED IN REGISTER 15
p+2           ..            /PROGRAM CONTINUES FROM THIS REGISTER
The previous contents of the a-register are lost The AC is not disturbed, and the contents of the register containing the operand are not changed.

XSK - Index and Skip

Form: XSK I a
Octal code: 0200 + 20I + a
Execution time: 3.2 µsec
Operation: If I=1, the contents of the designated a-register are incremented by 1, using 10-bit 2's complement addition as in B-class indexing. If I=0, a are left undisturbed. Then, if the contents of bits 2-11 of the a-register are equal to 1777, the next instruction in the program sequence is skipped. Otherwise, the skip does not occur.

When C(a) are incremented, the two high- order bits are not affected. Thus, 1777 is incremented to 0000, 3777 to 2000, etc.

PROGRAM CONTROL

JMP - Jump

Form: JMP Y
Octal code: 6000 + Y
Execution time: 3.2 µsec when Y != 0000; 1.6 µsec when Y = 0000
Operation: The quantity Y is placed in bits 2-11 of the Program Counter, the next instruction is taken from register Y. The program proceeds from that point.

If Y != 0000, the 10-bit address of the register immediately following the JMP instruction, i.e., the contents of the Program Counter, is stored in location 0000 of the instruction Field. as a JMP instruction. This permits the JMP to be used not only as an unconditional transfer of program control, but also as a subroutine calling instruction. (See the example below.)

If Y = 0000, the jump is executed, but nothing is stored in register 0000. JMP 0 is used to return from a subroutine. as shown in the example.

Example:

Address    Contents                   Action

0000        0000              /WILL CONTAIN 6573 AFTER JMP 175
 ...                          /IS EXECUTED
 ...
0175         ...              /START Of SUBROUTINE
 ...
 ...
0242        JMP 0             /RETURN FROM SUBROUTINE
 ...
 ...
0572        JMP 175           /JUMP TO SUBROUTINE AT REGISTER 0175
0573        ...               /SUBROUTINE RETURNS TO THIS LOCATION
When JMP 175 is executed, C(PC[2:11]) = 0573. This, combined with 6000, the octal code for JMP, is placed in register 0000. When the subroutine has finished, the JMP 0 transfers program control to register 0000, where JMP 573 is executed, returning control to the calling program. (At the same time, JMP 1 is stored in register 0000, but that is incidental to the actions of interest here.)

When a new instruction Field has been selected (see MEMORY ADDRESS CONTROL), the first JMP Y (Y != 0000) following the field selection performs the actual switching of the field: the target register of the JMP is in the new field, and the return jump is stored in register 0000 of the new instruction Field. JMP 0 has no effect on the field registers.

SHIFT AND ROTATE OPERATIONS

These instructions rotate the contents of the Accumulator left or right, or shift them right (scaling), propagating the sign bit. A single instruction can cause a shift of up to 17(8), bit positions. or 1½ times the width of the AC. On shifts or rotations right, the MQ is treated as a 12-bit extension of the AC, so that bits shifted out of AC[11] enter MQ[0] as shown in Figures 3-6, 3-7, and 3-8.

In all these operations, the Link is included when I = 1, and excluded when I = 0. Execution times depend on the length of the shift.

ROL - Rotate Left

Form: ROL I N
Octal code: 0240 + 20I + N, 0 <= N <= 17(8)
Execution time: 1.6 - 7.0 µsec
Operation: The contents of the AC are rotated left N places. If I=1, the Link is included. The rotation scheme is shown in Figure 3-6. The contents of the MQ are not affected.

                             I = 0

           +----------------------------------------+
       L   |  0               AC                11  |
      +-+  | +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  |
      | |  +-| | | |<--| | | |<--| | | |<--| | | |<-+
      +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+


                             I = 1

    +-----------------------------------------------+
    |  L      0               AC                11  |
    | +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  |
    +-| |<---| | | |<--| | | |<--| | | |<--| | | |<-+
      +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+

Figure 3-6. Rotate Left

ROR - Rotate Right

Form: ROR I N
Octal code: 0300 + 20I + N, 0 <= N <= 17(8)
Execution time: 1.6 - 5.0 µsec
Operation: The contents of the AC are rotated right N places. Bits shifted out of AC[11] enter MQ[0] and are shifted down the MQ. Bits shifted out of MQ[11] are lost. If I=1, the Link is included in the rotation. The scheme is shown in Figure 3-7.

                             I = 0

          +-----------------------------------------+
       L  |   0               AC                11  |
      +-+ |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  /
      | | +->| | | |-->| | | |-->| | | |-->| | | |->
      +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  \
                                                    |
          +-----------------------------------------+
          |   0               MQ                11  
          |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
          +->| | | |-->| | | |-->| | | |-->| | | |--> LOST
             +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+


                             I = 1

   +------------------------------------------------+
   |   L      0               AC                11  |
   |  +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  /
   +->| |--->| | | |-->| | | |-->| | | |-->| | | |->
      +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  \
                                                    |
          +-----------------------------------------+
          |   0               MQ                11  
          |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
          +->| | | |-->| | | |-->| | | |-->| | | |--> LOST
             +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+

Figure 3-7. Rotate Right

SCR - Scale Right

Form: SCR I N
Octal code: 0340 + 20I + N, 0 <= N <= 17(8)
Execution time: 1.6-5.0 microseconds
Operation: The contents of the AC are shifted right N places. The sign bit (contents of AC[0]) is not changed, and is replicated in the N bits to the right of AC[0]. Bits shifted out of AC[11] enter MQ[0] and are shifted down the MQ. Bits shifted out of MQ[11] are lost. If I=1 bits shifted out of AC[11] also enter the Link, so that at the completion of the operation, C(L)=C(MQ[0]). If I=0, the Link is unaffected. The shifting scheme is shown in Figure 3-8.

Example:

C(AC)= 4371            C(MQ)= 0000

Instruction:           SCR I 6
Because I = 1, the Link will receive the contents of AC[11] at each shift of position. The result of the operation:
C(AC)= 7743           The sign bit, which was 1, was replicated in the
                      vacated bits (AC[1:6])

C(MQ)= 7100           Bits shifted out of the AC entered the MQ at the
                      high- order end.

C(L)= 1               The last bit shifted out of AC[11] was a 1.
                      Check: C(L)= C(MQ[0]).



                             I = 0


       L      0               AC                11 
      +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
      | | +->| | | |-->| | | |-->| | | |-->| | | |->
      +-+ |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  \
          |   |                                     |
          +---+                                     |
          +-----------------------------------------+
          |   0               MQ                11  
          |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
          +->| | | |-->| | | |-->| | | |-->| | | |--> LOST
             +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+


                             I = 1

   +------------------------------------------------+
   |   L      0               AC                11  |
   |  +-+    +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  /
   +->| | +->| | | |-->| | | |-->| | | |-->| | | |->
      +-+ |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+  \
          |   |                                     |
          +---+                                     |
          +-----------------------------------------+
          |   0               MQ                11  
          |  +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
          +->| | | |-->| | | |-->| | | |-->| | | |--> LOST
             +-+-+-+   +-+-+-+   +-+-+-+   +-+-+-+
Figure 3-8. Scale Right

SKIPS

These instructions test the states of various registers, flip-flops, and external inputs. In every case, the next succeeding instruction in the program sequence is skipped if:

(1) I = 0 and the condition is met
or
(2) I = 1 and the condition is not met

Otherwise, the program proceeds without skipping.

APO - Accumulator Positive

Form: APO I
Octal code: 0451 + 20I
Execution time: 1.6 µsec Condition: The sign bit (contents of AC[0]) is 0, that is, C(AC) is a positive number.

AZE - Accumulator Zero

Form: AZE I
Octal code: 0450 + 20I
Execution time: 1.6 µsec
Condition: The contents of the AC equal 0000 (+0) or 7777 (-0)

LZE - Link Zero

Form: LZE I
Octal code: 0452 + 20I
Execution time: 1.6 µsec
Condition: The contents of the Link equal 0.

QLZ - MQ Low-Order Bit Zero

Form: QLZ I
Octal code: 0455 + 20I
Execution time: 1.6 µsec
Condition: The contents of MQ[11] equal 0. (This is identical to the LINC-8 instruction, ZZZ.)

FLO - Overflow

Form: FLO I
Octal code: 0454 + 20I
Execution time: 1.6 µsec
Condition: The overflow flip-flop (FLO FF) is set to 1. When overflow occurs as the result of an addition (ADD, ADA, ADM, or LAM), FLO FF is set to 1. When no overflow occurs, FLO FF is cleared.

The following skips test for various external input conditions.

SNS - Sense Switch

Form: SNS I N
Octal code: 0440 + 20I + N, 0 <= N <= 5
Execution time: 1.6 µsec
Condition: Sense Switch N on the Operator's Console is set to 1. If I=1, the skip will occur when the selected switch is set to 0.

SXL - Skip On External Level

Form: SXL I N
Octal code: 0400 + 20I + N, 0 <= N <= 17(8)
Execution time: 1.6 µsec
Condition: An external input level is +3v. If I=1, the skip will occur when the external level is at ground (0V). In the basic PDP-12, only three of these levels have been defined; the others are available for the user's options. These external levels are digital inputs to the I/O bus, and should not be confused with the analog inputs to the A-D Converter.

NOTE

The connection for the External Level Lines is made in the I/O Bus cables (See Chapter 5).

The three defined levels and their mnemonics are:

SXL I 15 (KST): Key Struck (See below)
SXL I 16 (STD): Tape Instruction Done (See Section VI)
SXL I 17 (TWC): Tape Word Complete (See Appendix A)

KST - Key Struck

Form: KST I
Octal code: 0415 + 20I
Execution time: 1.6 µsec
Condition: A key has been struck on the ASR-33 keyboard, the character code has been assembled in the Teletype buffer, and the Keyboard flag is raised. (The flag is cleared when the character is read into the AC).

MISCELLANEOUS

These instructions perform various tasks. Each is self-contained; they require no memory references, and the I-bit has no effect.

HLT - Halt

Octal code: 0000
Execution time: 1.6 µsec to fetch and decode
Operation: The computer stops. The contents of the AC, MQ, Link, and other active registers and flip- flops are not affected. The Program Counter contains the address of the register immediately following the HLT. If the operator presses CONTINUE, the program resumes from the point indicated by the C(PC).

CLR - Clear

Octal code: 0011
Execution time: 1.6 µsec
Operation: The AC, MQ, and Link are cleared to zero. No other registers or flip-flops are affected.

COM - Complement AC

Octal code: 0017
Execution time: 1.6 µsec
Operation: The contents of the AC are complemented. Bits containing zeros are changed to contain 1's, and vice versa. No other registers are affected.

NOP - No Operation

Octal code: 0016
Execution time: 1.6 µsec
Operation: None. Nothing happens. NOP provides a 1.6 microsecond delay and is often used to hold a place in the program for instructions which might be changed during the course of execution.

QAC - Place MQ in AC

Octal code: 0005
Execution time: 1.6 µsec
Operation: The contents of bits 0-10 of the MQ are placed in bits 1-11 of the AC. AC[0] is cleared. This instruction provides access to the low-order bits of a fractional product. Figure 3-9 shows the transfer path.

      +---+---+---+---+---+---+---+---+---+---+----+----+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
      +---+---+---+---+---+---+---+---+---+---+----+----+
Set to  |   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^    ^
  zero -+   |   |   |   |   |   |   |   |   |   |    |
          +---+---+---+---+---+---+---+---+---+---+----+----+
          | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
          +---+---+---+---+---+---+---+---+---+---+----+----+
Figure 3-9. QAC Transfer Path

To obtain all 12 bits of the MO, the following program sequence may be used:

Instruction               Action

QAC         /C(MQ[0:10]) PLACED IN AC[1:11]
ROL 1       /ROTATE C(AC) LEFT 1 PLACE, WITHOUT LINK.
QLZ I       /SKIP IF C(MQ[11])= 1
JMP .+3     /C(MQ[11])=0. JUMP TO THIRD REGISTER BEYOND.
BSE I       /C(MQ[11])=1. SET AC[11] EQUAL TO 1.
0001        /OPERAND TO SET AC[11]
(QAC is identical to the LINC-8 instruction, ZTA).

CONSOLE SWITCHES

These instructions provide access to the states of the switches in the Left and Right Switch Registers on the Operator's Console. The I-bit has no effect in these instructions.

LSW - Left Swifches

Octal code: 0517
Execution time: 1.6 µsec
Operation: The contents of the Left Switches Register on the Console are placed in the AC. The previous C(AC) are lost.

RSW - Right Switches

Octal code: 0516
Execution time: 1.6 µsec
Operation: The contents of the Right Switches Register are placed in the AC. The previous C(AC) are lost.

MODE CONTROL

PDP - Switch To PDP-8 Mode

Octal code: 0002
Execution time: 1.6 microseconds
Operation: Beginning with the next succeeding instruction, the central processor will operate in PDP-8 mode; all subsequent instructions are interpreted as PDP-8 operations. A similar instruction, LINC, in the PDP-8 mode instruction set, causes a switch to LINC mode.

Input/Output Bus

In addition to the input and output devices controlled directly by LINC instructions (see Sections IV, V, and VI), the LINC mode program also has direct access to any device connected to the PDP-12 I/O Bus. By using the special enabling instruction, IOB, he may include any PDP-8 mode IOT command within his LINC program sequence.

This access is provided by the special two-word instruction, IOB.

IOB - I/O Bus Enable

Form: IOB (first word) IOT(second word)
Octal code: 0500 (first word)
Execution time: 5.9 µsec
Operation: The IOT timing chain is activated by the second word of this instruction. Bits 3-11 of this second word are interpreted as a PDP-8 IOT command; bits 0-2 have no effect.

Example 1:

The following sequence may be used to read and store a character from the high- speed tape reader:

         ...
         IOB                  /ENABLE I/O BUS
         RRB                  /READ TAPE READER BUFFER
         STA 14               /STORE IN REGISTER SPECIFIED BY C(0014)
         ...
Example 2:

The following sequence tests the high-speed reader flag:

         ...
         IOB                  /ENABLE I/O BUS
         RSF                  /SKIP IF HIGH-SPEED READER FLAG IS SET
         JMP .-2              /NOT SET. GO BACK TWO SPACES.
         IOB                  /FLAG IS SET. ENABLE THE BUS, AND ...
         RRB                  /... READ THE CHARACTER.
Several IOB/IOT pairs are used in LINC Memory Address Control and Program interrupt operations.

NOTE

In the skip loop, the program must jump back two locations, because the IOB must be executed each time.

MEMORY ADDRESS CONTROL

The two memory field segments used by a LINC program are program-selectable. The assignments are made by setting the two 5-bit Memory Field Registers, which can address any of 32 1024- word memory segments. Considered with respect to the physical configuration of memory, the three high-order bits of each Field Register determine which 4096- word memory bank is to be used, while the two low-order bits specify one of the four segments within that bank The two LINC memory fields need not be adjacent, in any particular order, or even in the same memory bank. Normally, however, they would not be assigned to the same segment.

In addition to the Instruction Field (IF) and Data Field (DF) Registers described in Chapter 1, the PDP-12 Memory Control contains two other registers of interest to the LINC-mode programmer.

Instruction Field Buffer (IB) 5 Bits

This register holds the number specifying a new instruction Field. Once loaded, its contents are transferred to the IF at the occurrence of the next JMP Y instruction.

Save Field Register (SF) 10 Bits

NOTE

For historical reasons the SF is also called Interrupt Buffer in some places.

Whenever the instruction Field is changed, either by programmed action or by a program interrupt or trap, the contents of the IF and DF are placed in the Save Field Register. From the SF, the contents of the IF and DF can be restored, so that execution of an interrupted program, for example, can be resumed. The contents of the SF can be read into the AC.

Memory Control Programming

The Instruction Field and Data Field registers can he loaded directly, using LINC mode instructions.

LIF - Load LINC Instruction Field Buffer

Form: LIF N
Octal code: 0600 + N, 0 <= N <= 37(8)
Execution time: 1.6 µsec
Operation: The five-bit quantity N is placed in the instruction Field Buffer (IB). The present contents of the IF and DF are transferred to the Save Field Register (SF). When the next JMP Y instruction (Y != 0000) is executed, N is transferred from the IB to the Instruction Field Register. The return JMP is stored in location 0000 of the new instruction Field, and program control is transferred to register Y of the new instruction Field.

The automatic saving of the IF and DF in the Save Field Register is especially useful when subroutines are called across memory fields - that is, when a subroutine located in a memory field other than the current one is called. The calling program can ignore the problem of transmitting to the subroutine the memory field information which the subroutine requires to obtain arguments of the call and to return control to the calling program after the subroutine has run to completion. This information is available to the subroutine by virtue of the field-saving property of the instruction LIF.

The execution of the LIF instruction will internally inhibit the execution of a Program interrupt even if ION has been given. This Interrupt inhibit lasts from the LIF instruction until the first LINC mode JMP instruction executed in the newly selected instruction Field. The above property allows the Save Field Register to be used for cross field subroutine linkage in programming which uses the Program Interrupt.

Example: The program is operating in Field 2 Control is to be transferred to location 1000 of Field 5.

Address      Action                               Contents

...
p             LIF 5             /5 IS PLACED IN THE IB
                                /C(IF) AND C(DF) ARE PLACED IN THE SF.
...
p+k           JMP 1000          /C(IB) ARE TRANSFERRED TO THE
                                /IF. JMP P+K+1 IS STORED IN REGISTER
                                /0000 OF FIELD 5, AND THE PROGRAM
                                /PROCEEDS FROM REGISTER 1000 OF FIELD 5.
JMP 0 has no effect on the Memory Field registers. If it is used to return to a calling program in a different field, the change of field is effected by the JMP instruction stored in register 0000 of the subroutine's field.

(LIF replaces the LINC-8 instruction, LMB)

LDF - Load LINC Data Field Register

Form: LDF N
Octal code: 0640 + N, 0 <= N <= 37(8)
Execution time: 1.6 µsec
Operation: The 5-bit quantity N is placed in the Data Field Register. All subsequent indirect references to the Data Field are made to the newly selected field. The previous C(DF) are lost. The contents of the other Memory Control registers are not affected.

(LDF is identical to the LINC-8 instruction, UMB)

The contents of the Memory Field Registers can be examined by using the following IOB/IOT pairs.

IOB
RIF - Read Instruction Field

Octal code: 0500 6224
Execution time: 5.9 µsec, including IOB
Operation: The contents of the instruction Field Register are placed in bits 6-10 of the AC. The remaining AC bits are unaffected, and the contents of the IF are unchanged.

IOB
RDF - Read Data Field

Octal code: 0500 6214
Execution time: 5.9 µsec, including IOB
Operation: The contents of the Data Field Register are placed in bits 6-10 of the AC. The remaining AC bits are unaffected, and the contents of the DF are not changed.

Inst. Field       +---+---+---+---+---+
     Buffer       | 0 | 1 | 2 | 3 | 4 |
                  +---+---+---+---+---+
                    |   |   |   |   |
                    V   V   V   V   V  <--JMP after LIF
                  +---+---+---+---+---+   +---+---+---+---+---+
Inst. Field       | 0 | 1 | 2 | 3 | 4 |   | 0 | 1 | 2 | 3 | 4 |  Data Field
                  +---+---+---+---+---+   +---+---+---+---+---+
                     |   |   |   |   |     |   |   |   |   |  <--Interrupt,
                     V   V   V   V   V     V   V   V   V   V     Trap, LIF
                    +---+---+---+---+---+---+---+---+---+---+
                    | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
                    +---+---+---+---+---+---+---+---+---+---+
                      |   |   |   |   |   |   |   |   |   |
      +---------------|---|---|---|---|---|---|---|---+   |  <-- IOB or RIB
      |   +-----------|---|---|---|---|---|---|---|-------+      Instruction
      |   |           |   |   |   |   |   |   |   |
      V   V           V   V   V   V   V   V   V   V
    +---+---+       +---+---+---+---+---+---+----+----+
AC  | 0 | 1 |       | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
    +---+---+       +---+---+---+---+---+---+----+----+
Figure 3-10. Data Path: IB, IF, DF, and AC

PROGRAM INTERRUPT IN LINC MODE

To facilitate the handling of data being transmitted to and from several peripheral devices, the PDP-12 includes a Program Interrupt Facility. When an external device is ready for servicing, a signal (flag) associated with that device is set. If the interrupt is enabled at the time a flag is raised, the following sequence of events will occur:

  1. The instruction being executed at the time of the interrupt request is completed.

  2. The contents of the Program Counter are stored in register 0040 of memory field 0 (regardless of the current Instruction Field assignment).

  3. The contents of the Memory Field registers are placed in the Interrupt Buffer, as shown in Figure 3-10.

  4. Program execution proceeds from register 0041 of Memory Field 0.

The normal procedure from this point calls for the interrupt service routine beginning in location 0041 to determine which device flag caused the interrupt request, perform the appropriate tasks, then restore the Memory Field registers, re-enable the interrupt, and jump back to the interrupted program at the point of the Program Interrupt.

The interrupt control instructions and related memory field instructions are all IOB/IOT pairs.

Whenever a change of LINC Instruction Field occurs, the Program Interrupt is inhibited until the first JMP is executed in the new field. This allows the programmer to obtain and save the contents of the SF after the Field change, before a waiting interrupt request destroys the contents of the SF.

IOB
ION - Interrupt On

Octal code: 0500 6001
Execution time: 5.9 µsec including IOB
Operation: The Interrupt Facility is enabled immediately after the next succeeding instruction (following the ION) is executed. From that point on, any interrupt request will cause the sequence of events described above. If a device flag is already raised when the Interrupt is enabled, the waiting request is serviced immediately. A one- instruction delay before enabling the interrupt ensures that the interrupt service routine can return to an interrupted program before a new request is honored, so as to avoid losing one's place.

IOB
IOF - Interrupt Off

Octal code: 0500 6002
Execution time: 5.9 µsec, including IOB
Operation: The interrupt is disabled. The facility is disabled immediately; subsequent request will not cause an interrupt until the facility is enabled again.

The next two instructions are related to the Save Field Register, wherein the original contents of the IF and DF are stored whenever the contents of the IF are being changed, by an LIF instruction, or as the result of an interrupt request, or as the result of a Program Trap.

IOB
RIB - Read Interrupt Buffer

Octal code: 0500 6234
Execution time: 5.9 µsec, including IOB
Operation: The contents of the Interrupt Buffer (Save Field Register) are OR'ed into bits 0-1 and 4-11 of the AC, as shown in Figure 3-10. Bits 2 and 3 of the AC, and the contents of the SF are unchanged.

RIB is most commonly used immediately after a change of instruction field or a program trap, to save the record of the origin fields while the Program interrupt is inhibited. (The first JMP instruction executed after a trap or change of instruction field restores the interrupt; a waiting request would destroy the contents of the Save Field Register.)

IOB
RMF - Restore Memory Fields

Octal code: 0500 6244
Execution time: 5.9 µsec, including IOB
Operation: The contents of bits 5-9 of the SF are placed in the Data Field Register, and the contents of bits 0-4 of the SF are placed in the Instruction Field Buffer. At the next occurrence of a JMP Y instruction (Y != 0000), the contents of the IB are transferred to the IF, effecting a return to the proper field after servicing an interrupt request. The data transfer path is shown in Figure 3-11.

DJR - Disable JMP Return Save

Octal code: 0006
Execution time: 1.6 µsec
Operation: DJR sets a flip-flop which prevents the modification of location 0000 when the next and only the next LINC mode JMP is given. The DJR instruction is used when returning from Program Interrupt or Trap service routines. The DJR should be given prior to the ION of a return from Program Interrupt Servicing.

            Instruction Field
          +---+---+---+---+---+
          | 0 | 1 | 2 | 3 | 4 |
          +---+---+---+---+---+ Data Field Register
            ^   ^   ^   ^   ^ +---+---+---+---+---+
JMP Y -->   |   |   |   |   | | 0 | 1 | 2 | 3 | 4 |
            |   |   |   |   | +---+---+---+---+---+
          +---+---+---+---+---+ ^   ^   ^   ^   ^
      IB  | 0 | 1 | 2 | 3 | 4 | |   |   |   |   |
          +---+---+---+---+---+ |   |   |   |   |
            ^   ^   ^   ^   ^   |   |   |   |   | <--RMF
            |   |   |   |   |   |   |   |   |   |
          +---+---+---+---+---+---+---+---+---+---+
          | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
          +---+---+---+---+---+---+---+---+---+---+
            Save Field Reister
Figure 3-11. Data Path, RMF Instruction

Example: A program operating in Field 7 is interrupted while the instruction in register 0531 is being executed.

  1. C(PC) are stored in location 0040 of Field 0.

  2. C(DF) and C(IF) are placed in the SF, as shown in Figure 3-10.

  3. Program execution resumes in location 0041 of Field 0; in other words, 00 is placed in the IF, and 0041 in PC[2:11].

  4. The interrupt is disabled.

The interrupt service routine must do three things. First, it must set up a return jump to enable the program to get back to the point of the break. Next, it must identify the cause of the request and service the condition. Finally, it must restore the conditions prevailing at the time the interrupt occurred, and return to the main program. The following sequence shows how these tasks may be accomplished.

Address           Contents                                     Action

0040          0532                /CONTENTS OF PC AT TIME OF INTERRUPT
0041          STC ACSAV           /SAVE C(AC), THEN CLEAR AC
0042          ADD 0040            /SAVED ADDRESS (0532) TO AC
0043          BSE I               /MAKE JMP INSTRUCTION: C(AC) V C(0044)
0044          6000                /OCTAL CODE OF JMP
0045          STC RTN             /STORE JMP 532 AT END OF SERVICE ROUTINE
...           ...                 /MAIN PART OF SERVICE ROUTINE. IF NECESSARY,
...           ...                 /OTHER ACTIVE REGISTERS (MO, L, ETC.) SHOULD
...           ...                 /BE SAVED ALSO.
              IOB                 /EXIT SEQUENCE. ENABLE IOT TIMING CHAIN ...
              RMF                 /... AND RESTORE MEMORY FIELDS. (07 to IB)
...           STC TEMP            /CLEAR AC WITHOUT DISTURBING MQ AND L.
              ADD ACSAV           /RESTORE ORIGINAL C(AC)

              DJR                 /SET PROCESSOR SO THAT NEXT JMP INST WILL
                                  /NOT STORE IN LOCATION ZERO OF MEMORY BANK
                                  /TO WHICH JMP AT "RTN" WILL GO.

              IOB
              ION                 /RE-ENABLE INTERRUPT
RTN           (JMP 0532)          /JUMP TO ORIGINAL FIELD.
SPECIAL FUNCTIONS

A set of six Special Functions allows the LINC programmer to establish any of five operating states, or generate an I/O Preset pulse. The special functions are determined by bits 2-7 of the AC, as shown in Figure 3-12.


          +---+---+---+---+---+---+---+---+--
      AC  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | -
          +---+---+---+---+---+---+---+---+--
                    |   |   |   |   |   |
  Instruction       |   |   |   |   |   |       I/O Preset
         Trap ------+   |   |   |   |   +-----  Pulse
                        |   |   |   |
         Tape           |   |   |   |           Disable Teletype
         Trap ----------+   |   |   +---------  Interrupt
                            |   |
    Character               |   |               Fast
         Size --------------+   +-------------  Sample
Figure 3-12. Special Functions

The functions have the following characteristics:

  1. Instruction Trap Enable. Causes a program trap to register 0141 whenever one of these categories of LINC instruction codes is encountered: The instruction trap is described in detail in paragraph 3.25.

  2. Tape Trap. When this function and instruction Trap Enable are both set, a program trap to register 0141 will occur whenever a LINCtape instruction is encountered, in addition to the other trapped codes. The LINCtape instruction is not executed. Tape Trap is described in detail in Section VI.

  3. Character Size. This function determines the size of a character displayed on the CRT by the DSC instruction. It is described in detail in Section IV.

  4. Fast Sample. This function reverses the order of events of the SAM instruction, (i.e., read the converter buffer and then initiate a new conversion).

  5. Disable Teletype Interrupt. Interrupt requests from the ASR-33 Keyboard or Printer are inhibited. No program interrupt will occur, even if the Interrupt Facility has been enabled, and either TTY flag is set.

  6. Generate I/O Preset. If this bit is set when the enabling instruction (ESF) is executed, an I/O PRESET pulse is generated which clears all device flags, disables the Interrupt, clears the Tape Extended Operations Buffer, and generates the TAPE PRESET pulse. The effect is the same as if the I/O PRESET key on the Operator's Console were pressed. Other Special Functions are cleared, or in the case of CHARACTER SIZE, reset to 1. The active registers of the Central Processor are not affected, and the system continues to operate with RUN on.

Any or all of these functions may be enabled at the same time, except that they are effectively nullified if I/O PRESET is also enabled. All the Special Functions except I/O PRESET are controlled by flip-flops from the designated AC bits; the states of these flip-flops may be examined at any time.

ESF - Enable Special Functions

Octal code: 0004
Execution time: 1.6 µsec
Operation: The contents of AC bits 2-6 are placed in their respectively designated function flip-flops, as shown in Figure 3-12. For each AC bit set to 1, the corresponding function is enabled. For each AC bit set to 0, the corresponding function is disabled. If AC[7] is set to 1, the I/O PRESET pulse is generated.

SFA - Place Special Function Flip-Flops in AC

Octal code: 0024
Execution time: 1.6 µsec
Operation: The contents of the Special Function flip-flops are placed in their respectively designated AC bits, as shown in Figure 3-12. Bits 0, 1, and 7-11 of the AC are cleared.

INSTRUCTION TRAP

Several sets of operation codes in the LINC repertoire are undefined. The LINC programmer can make use of these codes, without having to hard-wire them, by means of subroutines and the Instruction Trap. When the Trap is enabled (ESF with C(AC[2])=1) all undefined LINC codes will cause a program trap. When the undefined code is encountered, program control is transferred to register 0141 of Memory Field 0, regardless of the current setting of the IF. The contents of the Program Counter are placed in register 140, and the contents of the IF and DF are are placed in the Save Field Register. The subroutine beginning on 0141 can examine the trapped code (using the information stored in 0140 and the SF) to determine what program- defined operations are to be performed.

These are the undefined LINC codes which cause a program trap:

The most common use of the Instruction Trap is probably in the execution of programs written for the LINC-8. To facilitate the use of such programs, a LINC-8 Simulator is provided in the basic PDP-12 software package. Close study of this program, will be most helpful for the programmer using the Trap facility.

Tape Trap

When both the Tape Trap and Instruction Trap functions are enabled, the LINCtape instructions (codes 700-737) are also trapped. This is useful when the programmer wishes to substitute another external storage device, such as a Disk, for the LINCtape.

Program Interrupt and Instruction Trap

If the interrupt is enabled when an Instruction Trap occurs, the interrupt is inhibited until the execution of the first JMP after the trap. This permits the trap program to store the contents of the Save Field Register immediately after the trap, so that the record of where the trap took place is not destroyed by an interrupt request, which also causes the contents of the IF and DF to be placed in the SF.