There are six memory reference instructions: DCA, TAD, AND, ISZ, JMP, and JMS. All may use either direct or indirect addressing. When indirect addressing is specified, add 1.6 microseconds to the execution time.
DCA - Deposit and Clear Accumulator
Form: DCA Y
Octal code: 3000 + Y
Execution time: 3.2 µsec
Operation: The contents of the AC are deposited in register Y; the AC is
then cleared to 0000. The previous C(Y) are lost.
TAD - 2's Complement Add To Accumulator
Form: TAD Y
Octal code: 1000 + Y
Execution time: 3.2 µsec
Operation: The contents of Y are added to the contents of the AC, using 2's
complement addition. If there is a carry out of bit 0, the Link is
complemented; otherwise, the Link is unchanged. The previous contents of the
AC are lost; the contents of Y are not changed.
AND - Logical AND To Accumulator
Form: AND Y
Octal code: 0000 + Y
Execution time: 3.2 µsec
Operation: The contents of the AC and the contents of Y are combined according
to the Boolean AND relation, with the result left in the AC. The comparison
is made on each bit pair independent of the other bits in the two operands.
The truth table for the AND relation is shown below:
C(AC[j])
0 1
+------------
|
0 | 0 0
C(Y[j]) |
1 | 0 1
|
When corresponding bits of AC and Y are both 1, the result is 1. Otherwise, the result is 0. The previous C(AC) are lost; the C(Y) are unchanged.
ISZ - Increment And Skip If Zero
Form: ISZ Y
Octal code: 2000 + Y
Execution time: 3.2 µsec
Operation: The contents of Y are incremented by 1. If the result is 0000, the
next instruction in sequence is skipped; otherwise, the next instruction is
executed. The contents of the AC are not affected.
JMP - Jump
Form: JMP Y
Octal code: 5000 + Y
Execution time: 1.6 µsec
Operation: The address Y is placed the PC, and the next instruction is taken
from register Y; the program continues from that point. The contents of the
AC are not affected.
JMS - Jump To Subroutine
Form: JMS Y
Octal Code: 4000 + Y
Execution time: 3.2 µsec
Operation: The contents of the PC are stored in Y. The address Y + 1 is placed
in the PC, and the program continues from Y + 1. The contents of the AC are
not affected, To return from the subroutine to the point at which the JMS was
given (i.e., to the register immediately following the JMS), the instruction
JMP I Y is executed. The contents of Y are taken as the effective
address; since Y contains the PC stored at the time of the JMS, control
returns to the calling program.
This class is divided into two groups, I and II. Group I instructions include miscellaneous operations on the Accumultor and Link. Group II instructions include skips, the program halt, and access to the console switches.
Operate class instructions are microprogrammed; they may be combined to provide several operations within a single instruction. However, combinations can be made only within a group; operations from different groups cannot be combined. To ease this restriction, the operation CLA (Clear the AC) is available in both groups. All Operate class instructions require 1.6 microseconds for execution.
The microprogram structure of Group I instructions is shown in Figure 4-3. Any combination of these functions can be made, but the programmer must be aware of the order in which the operations are performed when the instruction is executed. This order is as follows:
Rotate 1
Rotate position if 0
Operation AC and L 2 positions
Code 7 CLA CMA Right if 1
/ \ / \ / \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
+---+---+---+---+---+---+---+---+---+---+----+----+
\ / \ / \ / \ / \ /
Contains CLL CML Rotate IAC
0 to AC and L
Specify Left
Group 1
Figure 4-3. Group 1 Operate Class Instruction Format
NOP - No Operation
Octal code: 7000
Operation: None. This instruction may be used to provide short delays
(1.6 microseconds per instruction) or to hold a place for instructions to be
inserted by the program.
CLA - Clear Accumulator
Octal code: 7200
Operation: The contents of the AC are cleared to 0000.
CLL - Clear Link
Octal code: 7100
Operation: The contents of the Link are cleared to 0.
CMA - Complement Accumulator
Octal code: 7040
Operation: The 1's complement of the contents of the AC replace the original
contents of the AC. Each bit that is 0 becomes 1, and vice versa.
CML - Complement Link
Octal code: 7020
Operation: The contents of the Link are complemented,
IAC - Increment Accumulator
Octal code: 7001
Operation: The contents of the AC are incremented by 1, using 2's-complement
arithmetic. A carry out of bit 0 is lost. The Link is unaffected.
RAR - Rotate Accumulator Right
Octal code: 7010
Operation: The contents of the AC and Link are rotated right one position. A
digit rotated out of AC[11] enters the Link; the bit rotated out of
the Link enters AC[0].
(See Figure 4-4.)
RTR - Rotate Two Places Right
Octal code: 7012
Operation: The contents of the AC and Link, taken as a 13-bit register, are
rotated two positions to the right.
(See Figure 4-4.)
RAL - Rotate Accumularor Left
Octal code: 7004
Operation: The contents of the AC and Link, taken as a 13-bit register, are
rotated one place to the left. A bit leaving AC[0] enters the
Link; a bit leaving the Link enters AC[11].
(See Figure 4-4.)
RTL - Rotate Two Places Left
Octal code: 7006
Operation: The contents of the AC and Link, taken as a 13-bit register, are
rotated two positions left.
(See Figure 4-4.)
+------------------------------------------------+
| L 0 AC 11 |
| +-+ +-+-+-+ +-+-+-+ +-+-+-+ +-+-+-+ |
+--| |<---| | | |<--| | | |<--| | | |<--| | | |<-+
+-+ +-+-+-+ +-+-+-+ +-+-+-+ +-+-+-+
+------------------------------------------------+
| L 0 AC 11 |
| +-+ +-+-+-+ +-+-+-+ +-+-+-+ +-+-+-+ |
+->| |--->| | | |-->| | | |-->| | | |-->| | | |--+
+-+ +-+-+-+ +-+-+-+ +-+-+-+ +-+-+-+
Figure 4-4. Rotation Scheme for RAR, RTR, RAL, RTL
The following combined operations have been given separate mnemonics for programming convenience.
STA - Set Accumulator (CLA + CMA)
Octal code: 7240
Operation: Clear, then complement the AC. Resulting C(AC)= 7777.
STL - Set Link (CLL + CML)
Octal code: 7120
Operation: Clear, then complement the Link. Resulting C(L)= 1.
CIA - Complement And Increment Accumulator (CMA + IAC)
Octal code: 7041
Operation: Complement the AC, then increment the result by 1. This gives
the 2's complement of the original C(AC). The 2's complement of a number is
defined as the 1's complement plus 1.
GLK - Get Link (CLA + RAL)
Octal code: 7204
Operation: Clear the AC, then rotate one place left, thus putting the contents
of the Link into AC[11]. This instruction is useful in multiple
precision arithmetic.
Other useful Combinations - The programmer can place a number of selected constants in the AC by combining Group I operations, as shown:
Combination Resulting C(AC) CLA IAC 0001 CLA STL RTL 0002 CLA STL IAC RAL 0003 CLA CLL IAC RTL 0004 CLA STL IAC RTL 0006 STA CLL RAL 7776 (-2) STA CLL RTI 7775 (-3) CLA STL RAR 4000 CLA STL RTR 2000 CLA IAC STL RTR 6000
The microprogram structure of Group II operations is shown in Figure 4-5. Any
of these operations may be combined, but again, the programmer must be aware
of the sequence of events. In addition, the sense of the skip instruction
determines the manner in which combined skips are interpreted. If bit 8
is 0, the logical OR of the tested conditions will cause a skip; if the
bit is 1, the logical AND of the conditions will cause the skip. In the
first case, this means that the skip will occur if any one of the conditions
tested is true; in the second case, the skip will occur only if all the
conditions tested are true. The various combinations are described in
paragraph 4.8.4.
SNA Determines
Operation or Sense
Code 7 CLA CMA of Skip HLT
/ \ / \ / \ / \ / \
+---+---+---+---+---+---+---+---+---+---+----+----+
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
+---+---+---+---+---+---+---+---+---+---+----+----+
\ / \ / \ / \ / \ /
Contains SMA SNL OSR Contains 0
1 to or or to specify
Specify SPA SZL Operate Class *
Group 2
* This bit distinguishes group II Operate Class instructions from the
optional EAE instructcions, in which this bit is set to 1.
Figure 4-5. Group II Operate Class Instruction Format
The sequence of events in a Group II instruction is as follows:
HLT occurs after all other specified operations have been performed.
CLA - Clear AC
Octal code: 7600
Operation: Clear the AC
SKP - Skip Unconditionally
Octal code: 7410
Operation: The next instruction in the program sequence is skipped.
SNL - Skip On Non-Zero Link
Octal code: 7420
Skip Condition: The contents of the Link equal 1.
SZL - Skip on Zero Link
Octal code: 7430
Skip condition: The contents of the Link equal 0.
SZA - Skip On Zero Accumulntor
Octal code: 7440
Skip condition: The contents of the AC equal 0000.
SNA - Skip On Non-Zero Accumulator
Octal code: 7450
Skip condition: The contents of the AC are not equal to 0000.
SMA - Skip On Minus Accumulator
Octal code: 7500
Skip condition: The contents of AC[0] equal 1. By convention, a
negative number is one in which the most significant digit is 1. Thus, all
numbers between 4000 and 7777, inclusive, are negative. The 2's complement
of such a number is its positive counterpart. In this sense, 7777 is
equivalent to -1; 4000 is equivalent to -4000. The 2's complement sum of a
number and its 2's complement is always zero.
SPA - Skip On Plus Accumulator
Octal code: 7510
Skip condition: The contents of AC[0] equal 0. By the convention
described above, a number is positive if its most significant digit is 0.
OSR - OR Switch Register With Accumulator
Octal code: 7404
Operation: The contents of the console switch register (Right Switches) are
combined with the contents of the AC by the logical inclusive OR relation;
the result is left in the AC. If either bit of a corresponding pair is set
to 1, the result is 1. The result is 0 only if both AC and SR bits are 0.
This instruction is normally used with CLA to obtain the actual status of
the Switches (see below).
HLT - Halt
Octal code: 7402
Operation: The processor stops. The PC contains the address of the register
following the HLT instruction. The contents of the other processor registers
are not affected.
LAS - Load Accumulator From Switches (CLA + OSR)
Octal code: 7604
Operation: Clear the AC, then OR the contents of the Right Switches with
C(AC). This places the status of the switches in the AC. If the switch is
set to 1, the corresponding AC bit is set to 1.
The possible skip combinations are listed, with the conditions for a skip to occur.
Combination Octal Code A skip will occur if
SZA SNL 7460 C(AC)= 0000, or C(L)= 1, or both
SZA SMA 7540 C(AC)= 0000, or C(AC[0])= 1, or both
SMA SNL 7520 C(AC[0])= 1, or C(L)= 1, or both
SZA SMA SNL 7560 C(AC) = 0000, or C(AC[0])= 1, or C(L)= 1,
or any, or all of these.
SNA SZL 7470 C(AC) != 0 and C(L) = 0
SNA SPA 7550 C(AC) != 0 and C(AC[0]) = 0
SPA SZL 7530 C(AC[0])= 0 and C(L)= 0
SNA SPA SZL 7570 C(AC) != 0000 and C(AC[0])=0 and C(L)=0
If CLA is combined with any skip, the AC is cleared after the conditions
have been tested.
These instructions, all of which have the basic operation code of 6000, are used to service all peripheral devices, enable and disable the program interrupt and the memory extension control, change from PDP to LINC programming mode, and provide maintenance operations for the LINCtape subprocessor. Most of these instructions are described in Chapter 5 with their associated devices. The program interrupt and memory extension control are discussed in Sections IV and VI of this chapter.
Mode Control - To change operating mode from PDP-8 to LINC, the following IOT instruction is used.
Octal code: 6141
Execution time: 4.25 µsec
Operation: Starting with the next succeeding instruction, the central
processor will operate in LINC mode.