PDP-12 User's Manual

CHAPTER 4
PDP-8 MODE PROGRAMMING

Section V. EXTENDED ARITHMETIC ELEMENT

OPERATION

The Extended Arithmetic Element (EAE), Type KE12, adds a complete automatic multiplication and division facility to the PDP-12. Programming is by means of PDP-8 mode instructions. The AC and MQ are used to accommodate full 24-bit products and dividends, and the remainder and quotient after a division. Shifting, normalizing, and register setup instructions are included.

All operands are treated as unsigned integers; the programmer must establish his own sign conventions. The normalizing instruction facilitates the writing of floating-point subroutines.

EAE INSTRUCTIONS

The EAE instruction set has a basic operation code of 7401; all functions are microprogrammed, as in Operate Class commands. The microprogram structure of the EAE class is shown in Figure 4-6.


                                                 Contains 1
          Operation                              to specify
        -- Code 74 --      MQA     MQL           EAE Group
      /              \    /   \   /   \             /  \
      +---+---+---+---+---+---+---+---+---+---+----+----+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
      +---+---+---+---+---+---+---+---+---+---+----+----+
                      \   /   \   /    \          /
                       CLA     SCA      \---+----/
                                            |
                                       1=SCL  2=MUY
                                       3=DVI  4=NMI
                                       5=SHL  6=ASR
                                       7=LSR
Figure 4-6. EAE Instruction Format

As with other microprogrammed instructions, EAE operations are performed in a given order. Operations can be combined in a single instruction, except that operations occurring at the same time cannot be combined with meaningful results.

The order of events is as follows:

  1. CLA
  2. MQA, MQL, SCA
  3. SCL, MUY, DVI, NMI, SHL, ASR. LSR

CLA - Clear AC

Octal code: 7601
Execution time: 1.6 µsec
Operation: Clear the AC. The MQ and Link are unaffected.

MQA - Place MQ in AC

Octal code: 7501
Execution time: 1.6 µsec
Operation: The contents of the MQ are ORed into the AC. The C(MQ) are unchanged.

NOTE

All twelve bits are transferred; this is not identical to the LINC mode QAC instruction (page 3-21).

MQL - Load MQ from AC

Octal code: 7421
Execution time: 1.6 µsec
Operation: The contents of the AC are placed in the MQ. The previous C(MQ) are lost. The AC is cleared at the end of the instruction.

SCA - SCA Step Counter To AC

Octal code: 7441
Execution time: 1.6 µsec
Operation: The contents of the step counter are ORed with the contents of bits 7-11 of the AC; the result is left in the AC. To obtain the actual step count, this can be combined with CLA (combined operation code: 7641).

All the rest of the EAE instructions except NMI require two words; the first contains the operation to be performed, the second contains the operand. In the following descriptions, the notation p+1 designates the register containing the operand.

SCL - Load Step Counter

Octal code: 7403
Execution time: 3.2 µsec
Operation: The complement of the contents of bits 7-11 of p+1 is placed in the SC.

MUY - Multiply

Octal code: 7405
Execution time: 8.0 µsec
Operation: The number in the MQ is multiplied by the number in register p+1. At the conclusion of this command the Link contains a 0. The most significant 12 bits of the product are in the AC and the least significant 12 bits are in the MQ.

DVI - Divide

Octal code: 7407
Execution time: 4.0 µsec to 9.0 µsec
Operation: The 24-bit dividend is held in the AC (most significant part) and MQ (least significant part); the divisor is in register p+1. At the conclusion of the division, the quotient is in the MQ, and the remainder in the AC. If the division was carried out, the Link is left clear. If either dividend or divisor is zero, the operation ends after one step, and the Link is set to 1, to indicate that a divide overflow occurred.

NMI - Normalize

Octal code: 7411
Execution time: 1.6 µSec + 0.32 µsec/step
Operation: The AC and MU are treated as a single 24-bit register. The combined contents of the AC and MQ are shifted left until C(AC[0]) differs from C(AC[1]). Bits shifted out of AC, enter the Link; bits shifted out of the Link are lost. Zeros enter MQ[11] and are shifted up the registers. At the end of the operation, the SC contains the number of shifts performed, this being the exponent of the normalized floating point fraction. The shift path is shown in Figure 4-7.

         - To be done -
Figure 4-7. Shift Path for NMI, SHL

SHL - Shift Left (Arithmetic)

Octal code: 7431
Execution time: 3.2 µsec + 0.33 µsec/step
Operation: The combined contents of the Link, AC and MQ are shifted left N+1 places, where N is the number contained in bits 7-11 of register p+1. Bits shifted out of the Link are lost; zeros are shifted into MQ[11] and up the registers. The shift path is identical with that for NMI, as shown in Figure 4-7.

ARS - Shift Right (Arithmetic)

Octal code: 7415
Execution time: 3.2 µsec + 0.33 µsec/step
Operation: The combined contents of the AC and MQ are shifted right N+1 places, where N is the number contained in bits 7-11 of register p+1.The sign bit (AC[0]) is replicated in all vacated bit positions, and is also placed in the Link. Bits shifted out of MQ[11] are lost, as is the previous C(L). The shift path is shown in Figure 4-8.

            - To Be Done -
Figure 4-8. Shift Path for ASR

LSR - Shift Right Logical

Octal code: 7421
Execution time: 3.2 µsec + 0.33 µsec/step
Operation: The contents of the AC are placed in the MQ. The previous C(MQ) are lost. The AC is cleared at the end of the instruction.

             To Be Done
Figure 4-9. Shift Path for LSR

EAE PROGRAMMING

Multiplication

Multiplication is performed as follows:

  1. Load the AC with the multiplier using the TAD instruction.
  2. Transfer the contents of the AC into the MQ using the MQL command.
  3. Give the MUY command.
Note that steps 2 and 3 can be combined into one instruction. The contents of the MQ are then multiplied by the contents of the next successive core memory address (p+l). At the conclusion of the multiplication the most significant 12 bits of the product are held in the AC and the least significant bits are held in the MQ. This operation takes a maximum of 8.0 microseconds; at the end of this time the next instruction is executed.

The following program examples demonstrate the operation of the EAE multiplication:

Multiplication of 12-Bit Unsigned Numbers

Enter with a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with high order half of product in a core memory location labelled HIGH, and with low order half of product in the AC. Program time is approximately 13 microseconds.

     MQL MUY                     /LOAD MQ WITH MULTIPLICAND, INITIATE
                                 /MULTIPLICATION
     MLTPLR                      /MULTIPLIER
     DCA HIGH                    /STORE HIGH ORDER PRODUCT
     MQA                         /LOAD AC WITH LOW ORDER PRODUCT

Multiplication of 12-Bit Signed Numbers, 24-Bit Signed Product

Enter with a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with signed 24-bit product in core memory locations designated HIGH LOW.

          CLL
          SPA                       /MULTIPLICAND POSITIVE?
          CMA CML IAC               /NO. FORM TWO'S COMPLEMENT
          MQL                       /LOAD MULTIPLICAND INTO MQ
          TAD MLTPLR
          SPA                       /MULTIPLIER POSITIVE?
          CMA CML IAC               /NO. FORM TWO'S COMPLEMENT
          DCA MLTPLR
          RAL
          DCA SIGN                 /SAVE LINK AS SIGN INDICATOR
          MUY                      /MULTIPLY
MLTPLR,   0                        /MULTIPLIER
          DCA HIGH
          TAD SIGN
          RAR                      /LOAD LINK WITH SIGN INDICATOR
          MQA
          SNL                      /IS PRODUCT NEGATIVE?
          JMP LAST                 /NO
          CLL CMA IAC              /YES
          DCA LOW
          TAD HIGH
          CMA SZL IAC
          DCA HIGH
          SKP
LAST,     DCA LOW

Division

Division is performed as follows:

  1. Load the 12 least significant bits of the dividend into the AC using the TAD instruction, then transfer the contents of the AC into the MQ using the MQL command.
  2. Load the 12 most significant bits of the dividend into the AC.
  3. Give the DVI command.
The 24-bit dividend contained in the AC and MQ is divided by the 12-bit divisor contained in the next successive core memory address (p+1). This operation takes a maximum of 7.8 microseconds and is concluded with a 12-bit quotient held in the MQ, the 12-bit remainder in the AC, and the Link holding a 0 if divide overflow did not occur. To prevent divide overflow, the divisor in the core memory must be greater than the 12 bits of the dividend held in the AC. When divide overflow occurs, the Link is set and the division is concluded after only one cycle. Therefore the instruction following the divisor in core memory should be an SZL microinstruction to test for overflow. The instruction following the SZL may be a jump to a subroutine that services the overflow. This subroutine may cause the program to type out an error indication, rescale the divisor or the dividend, or perform other mathematical corrections and repeat the divide routine.

The following program examples demonstrate the use of the EAE in division.

Division of 12-Bit Unsigned Numbers

Enter with a 12-bit unsigned dividend in the AC and a 12-bit unsigned divisor in core memory. Exit with remainder in core memory location labeled REMAIN and with the quotient in the AC.

          CLL
          MQL DVI                      /LOAD MQ,INITIATE DIVISION
          DIVISOR                      /DIVISOR
          SZL                          /OVERFLOW?
          JMP                          /YES,EXIT
          DCA REMAIN
          MQA                          /LOAD AC WITH QUOTIENT
Division Of 12-Bit Signed Numbers

Enter with a 12-bit signed dividend in the AC and a 12-bit signed divisor in core memory. Exit with unsigned remainder in core memory location REMAIN and a 12-bit signed quotient in the AC.

          CLL                         /DIVIDEND POSITIVE?
          SPA                         /NO
          CMA CML IAC
          MQL
          TAD .+11                     
          SPA                         /DIVISOR POSITIVE?
          CMA CML IAC                 /NO

          DCA .+6                     
          SNL                         /QUOTIENT NEGATIVE?
          CMA                         /NO
          CLL                         
          DCA SIGN                    /SET SIGN INDICATOR
          DVI
          DIVISOR                     /DIVISOR
          SZL                         /OVERFLOW
          JMP                         /EXIT ON OVERFLOW
          MQA
          ISZ SIGN
          CMA IAC