Because the processing power of the computer depends largely upon the range and number of peripheral devices that can be connected to it, the PDP-12 has been designed to interface readily with a broad variety of external equipment. The following chapter defines the interface characteristics of the computer to allow the reader to design and implement any electrical interfaces required to connect devices to the PDP-12.
The simple I/O technique of the PDP-12, the availability of DEC's FLIP CHIP logic circuit modules, and DEC's policy of giving assistance wherever possible allow inexpensive, straight forward device interfaces to be realized. Should questions arise relative to the computer interface characteristics, the design of interfaces using DEC modules, or installation planning, customers are invited to telephone any of the sales offices or the main plant in Maynard, Massachusetts. Digital Equipment Corporation makes no representation that the interconnection of its circuit modules in the manner described herein will not infringe on existing or future patent rights. Nor do the descriptions contained herein imply the granting of licenses to use, manufacture, or sell equipment constructed in accordance therewith.
The PDP-12 contains a processor and core memory composed of Digital's M- Series TTL circuit modules. These circuits have an operating temperature exceeding the limits of 50 F to 100 F, so no air-conditioning is required at the computer site. Standard 115V, 50/60-CPS power operates an internal solid state power supply that produces all required voltages and currents. High-capacity high-speed I/O capabilities of the PDP-12 allow it to operate a variety of peripheral devices in addition to the standard Teletype keyboard/printer, tape reader, and tape punch. DEC options, consisting of an interface and normal data processing equipment, are available for connecting into the computer system. These options include a random access disc file, card equipment, line printers, magnetic tape transports, magnetic drums, analog-to-digital converters, CRT displays, and digital plotters. The PDP-12 system can also accept other types of instruments or hardware devices that have an appropriate interface. Up to 61 devices requiring three programmed command pulses, or up to 183 devices requiring one programmed command pulse can be connected to the computer. Interfacing of any devices to the computer requires no modifications to the processor and can be achieved in the field.
Control of some kind is needed to determine when an information exchange is to take place between the PDP-12 and peripheral equipment and to indicate the location(s) in the computer memory which will accept or yield the data. Either the computer program or the device external to the computer can exercise this control. Transfers controlled by the computer, hence under control of its stored program, are called programmed data transfers.
Transfers made at times controlled by the external devices through the data break facility are called data break transfers.
Programmed Data Transfers
The majority of I/O transfers occur under control of the computer program. To transfer and store information under program control requires about six times as much computer time as under data break control. In terms of real time, the duration of a programmed transfer is rather small, due to the high speed of the computer, and is well beyond that required for laboratory or process control instrumentation.
To realize full benefit of the built-in control features of the PDP-12 programmed I/O transfers should be used in most cases. Controls for devices using programmed data transfers are usually simpler and less expensive than controls for devices using data break transfers. Using programmed data transfer facilities simultaneous operation of devices is limited only by the relative speed of the computer with respect to the device speeds, and the search time required to determine the device requiring service. Analog-to-digital converters, digital-to-analog converters, digital plotters, line printers, message switching equipment, and relay control systems typify equipment using only programmed data transfers.
Data Break Transfers
Devices which operate at very high speed or which require very rapid response from the computer use the data break facilities. Use of these facilities permits an external device, almost arbitrarily, to insert or extract words from the computer core memory, bypassing all program control logic. Because the computer program has no cognizance of transfers made in this manner, programmed checks of input data are made prior to use of information received in this manner. The data break is particularly well-suited for devices that transfer large amounts of data in block form, e.g., random access disc file, high-speed magnetic tape systems, high-speed drum memories, or CRT display systems containing memory elements.
It is sometimes very useful for a program to be able to initiate operation of an I/O device and then continue with execution of programming which is not immediately related to the input-output operation, rather than to wait for the device to become ready to transfer data. In this mode of operation, the device itself through use of the PDP-12 Program Interrupt facility initiates execution of the programming to transfer data to or from the computer. When the device requires service, i.e., when the device is ready to transfer data, it transmits an interrupt request signal to the computer. This signal causes the execution of the program currently underway to be interrupted, and program control to be transferred to a specific memory location. This location having been filled with a JMP to the starting point of a program to control the data transfer.
After completion of the data transfer, the interrupted program is resumed. The information needed to return to the interrupted program is saved at the time the program interrupt occurs. The program interrupt hardware is designed so that interrupt requests from devices may be ignored if the program so desires.
Logic Symbols The PDP-I2 uses TTL logic internally. In order to discuss some of the internal logic pertaining to interfacing, it is necessary to understand the TTL symbology used in the PDP-12. The logic symbols are shown in Figure 5-1.
All signals not originating at a flip-flop output are true when the line is at the level indicated by the suffix H (high) or L (low). Thus a line labeled IOP 1 H is high when the pulse is being generated and is otherwise ground. Similarly, AC CLEAR L is at ground for assertion, and positive otherwise.
Figure 5-1. Logic Symbols
Signals originating at flip-flops are defined in terms of the flip-flop state. The following table illustrates the convention.
Signal Name State of MB Flip-Flop Signal Voltage MB 03 (0)H 0 +3V MB 03 (0)L 0 0V MB 03 (1)L 1 0V MB 03 (1)H 1 +3V
Note: The line MB 03(0)H is the same line as MB 03(1)L and MB 03(1)H is the same line as MB 03(0)L.
PROGRAMMED DATA TRANSFERS AND I/O CONTROL
The majority of I/O transfers take place under control of the PDP-12 program taking advantage of control elements built into the computer. Although programmed transfers take more computer and actual time than do data break transfers, the timing discrepancy is insignificant, considering the high speed of the computer with respect to most peripheral devices. The maximum data transfer rate for programmed operations of 12-bit words is 148 kc when no status checking end transfer check, etc., is done. This speed is well beyond the normal rate required for typical laboratory or process control instrumentation.
The PDP-12 is a parallel-transfer machine that distributes and collects data in bytes of up to twelve bits. All programmed data transfers take place through the accumulator, the 12-bit arithmetic register of the computer. The computer program controls the loading of information into the accumulator (AC) for an output transfer, and for storing information in core memory from the AC for an input transfer. Output information in the AC is power amplified and supplied to the interface connectors for bussed connection to many peripheral devices. Then the program-selected device can sample these signal lines to strobe AC information into a control or information register. Input data arrives at the AC as pulses received at the interface connectors from bussed outputs of many devices. Gating circuits of the program-selected device produce these pulses. Command pulses generated by the device now to the input/output skip facility (IOS) to sample the condition of I/O device flags. The IOS allows branching of the program based upon the condition or availability of peripheral equipment, effectively making programmed decisions to continue the current program or jump to another part of the program, such as a subroutine that services an I/O device.
The bussed system of input/output data transfers imposes the following requirements on peripheral equipment.
Operation IOP Generator Code Control / \ / \ / \ / \ +---+---+---+---+---+---+---+---+---+---+---+---+ | | | | | | | | | | | | | | 6 | 3 | 4 | X | | | | | | | | | | | | | | +---+---+---+---+---+---+---+---+---+---+---+---+ \ / \ / Device Selection Code (34)Figure 5-2. IOT Instruction Decoding
Devices which require immediate service from the computer program, or which take an exorbitant amount of computer time to discontinue the main program until transfer needs are met, can use the program interrupt (PI) facility. In this mode of operation, the computer can initiate operation of I/O equipment and continue the main program until the device requests servicing. A signal input to the PI requesting a program interrupt causes storing of the conditions of the main program and initiates a subroutine to service the device. At the conclusion of this subroutine, the main program is reinstated until another interrupt request occurs.
Timing and IOP Generator
When the IR decoder detects an operation code of 6000(8) it identifies an IOT instruction and the computer generates a slow cycle. The Slow Cycle signal ANDS with TP4 to generate I/O Start and Sets the I/O PAUSE flip-flop. The logic of the IOP generator consists of a re-entrant delay chain which generates three time states. These time states are gated with MB bits 11, 10 and 9 to generate IOP 1, IOP 2 and IOP 4 respectively. Note that an IOP is generated only if the corresponding MB bit is set although the I/O timing remains constant. At the end of each IOP, the state of the I/O interface is sampled by an I/O strobe pulse.
Following the end of IOP 4 time, the PAUSE flip-flop is reset and the normal timing chain is restarted.
Unlike PDP8/I, the PDP-12 makes no timing distinction between internal I/O functions and normal I/O. Thus all I/O instructions cause the slow cycle.
Instruction IOP IOT Event Used Primarily For, Bit Pulse Pulse Time But Not Restricted To 11 IOP 1 IOT 1 1 Sampling Flags, Skipping. 10 IOP 2 IOT 2 2 Clearing Flags, Clearing AC. 9 IOP 4 IOT 4 3 Reading Buffers, Loading Buffers and Clearing Buffers.
Figure 5-3. Programmed Data Transfer Interface Block Diagram
Device Selector (DS)
Bits 3 through 8 of an IOT instruction serve as a device or subdevice select
code. Bus drivers in the processor buffer both the binary 1 and 0 output
signals of MB,~, and distribute them to the interface connectors
for bussed connection to all device selectors. Each DS is assigned a select
code and is enabled only when the assigned code is present in the MB. When
enabled, a DS regenerates IOP pulses as IOT command pulses and transmits these
pulses to skip, input, or output gates within the device and/or to the
processor to clear the AC.
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Figure 5-4. Programmed Data Transfer Timing
Each group of three command pulses requires a separate DS channel, and each DS channel requires a different select code (or I/O device address). One I/O device can, therefore, use several DS channels. Note that the processor produces the pulses identified as IOP 1, IOP 2, and IOP 4 and supplies them to all device selectors. The device selector produces pulses IOT 1, IOT 2, and IOT 4 which initiate a transfer or effect some control. Figure 5-5 shows generation of command pulses by several DS channels.
The logical representation for a typical channel of the DS, using channel 34, is shown in Figure 5-6. A 6 input NAND gate wired to receive the appropriate signal outputs from the MB,~s for select code 34 activates the channel. In the DS module, the NAND gate contains 8 input terminals; 6 of these connect to the complementary outputs of MB,_,, and 2 are open to receive subdevice or control condition signals as needed. Either the 1 or the 0 signal from each MB bit is connected to the NAND gate when establishing the select code. The ground level output of the NAND gate indicates when the IOT instruction selects the device, and can therefore enable circuit operations with the device. This output also enables three power NAND gates, each of which produces an output pulse if the corresponding IOT pulse occurs. The positive output from each gate is an IOT command pulse identified by the select code and the number of the initiating IOP pulse. Three inverters receive the positive IOT pulses to produce complementary IOT output pulses. An amplifier module can be connected in each channel of the DS to provide greater output drive.
Input/Output Skip (IOS)
Generation of an IOS pulse can be used to test the condition or status of a device flag, and to continue to or skip the next sequential instruction based upon the results of this test. This operation is performed by a 2-input AND gate in the device connected as shown in Figure 5-7. One input of the skip gate receives the status level (flag output signal), the second input receives an IOT pulse, and the output drives the computer skip (designated SKIP BUS L) to ground when the skip conditions are fulfilled. The state of the skip bus is sampled at the end of each IOT. If the bus has been driven to ground, the content of the program counter is incremented by 1 to advance the program count without executing the instruction at the current program count. In this manner an IOT instruction can check the status of an I/O device flag and skip the next instruction if the device requires servicing. Programmed testing in this manner allows the routine to jump out of sequence to a subroutine that services the device tested.
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Figure 5-5. Generation of IOT Command Pulses by Device Selectors
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Figure 5-6. Typical Device Selector (Device 34)
Assuming that a device is already operating, a possible program sequence to test its availability is:
100, 6342 /SKIP IF DEVICE 34 IS READY 101, 5100 /JUMP .-1 102, SXXX /ENTER SERVICE ROUTINE FOR DEVICE 34When the program reaches address 100, it executes an instruction skip with 6342. The skip occurs only if device 34 is ready when the IOT 6342 command is given. If device 34 is not ready, the flag signal disqualifies the skip gate, and the skip pulse does not occur. Therefore, the program continues to the next instruction which is a jump back to the skip instruction. In this example, the program stays in this waiting loop until the device is ready to transfer data, at which time the skip gate in the device is enabled and the skip pulse is sent to the computer IOS facility. When the skip occurs, the instruction in location 102 transfers program control to a subroutine to service device 34. This subroutine can load the AC with data and transfer it to device 34, or can load the AC from a register in device 34 and store it in some known core memory address.
- To be done -Figure 5-7. Use of IOS to Test the Status of an External Device
The binary 1 output signal of each flip-flop of the AC, buffered by a bus driver, is available at the interface connectors. These computer data output lines are bus connected to all peripheral equipment receiving programmed data output information from the PDP-12. A terminal on each flip-flop of the AC is connected to the interface connectors for bussing to all peripheral equipment supplying programmed data input to the PDP-12. An IOP that drives the AC input bus terminal to ground causes setting of the corresponding AC flip-flop to the binary 1 state. Output and input connections to the accumulator appear in Figure 5-8.
The status of the link bit is not available to enter into transfers with
peripheral equipment (unless it is rotated into the AC). A bus driver
continuously buffers the output signal from each AC flip-flop. These buffered
accumulator (BAG) signals are available at the interface connectors.
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Figure 5-8. Accumulator Input or Output
Input Data Transfers
When ready to transfer data into the PDP-12 accumulator, the device sets a flag connected to the IOS. The program senses the ready status of the flag and issues an IOT instruction to read the content of the external device buffer register into the AC. If the AC CLEAR BUS L is not asserted, the resultant word in the AC is the inclusive OR of the previous word in the AC and the word transferred from the device buffer register. The AC CLEAR BUS L may also be used as an I/O AC clear by activating only this line from a separate IOT.
The illustration in Figure 5-9 shows that the accumulator has an input bus for each bit flip-flop. Setting a 1 into a particular bit of the accumulator necessitates grounding of the interface input bus by the standard interface gate. In the illustration, the 2-input AND gates set various bits of the accumulator. In this case an IOT pulse is AND combined with the flip-flop state of the external device to transfer into the accumulator. (The program need not include a clear AC command prior to loading in this manner.)
Following the transfer (possibly in the same instruction) the program can
issue a command pulse to initiate further operation of the device and/or clear
the device flag.
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Figure 5-9. Loading Data into the Accumulator from an External Device
Output Data Transfers
The AC is loaded with a word (e.g., by a CLA TAD instruction sequence); then the IOT instruction is issued to transfer the word into the control or data register of the device by an IOT pulse (e.g., IOP 2), and operation of the device is initiated by another IOT pulse (e.g., IOP 4). The data word transferred in this manner can be a character to be operated upon, or can be a control word sampled by a status register to establish a control mode.
The BAC lines should be gated by the select code at each device to prevent excessive loading. A special module, the M101, is provided for this purpose.
Since the BAC interface bus lines continually present the status of the AC flip-flops, the receiving device can strobe them to sense the value in the accumulator. In Figure 5-10 a strobe pulse samples six bits of the accumulator to transfer to an external 6-bit data register. Since this is a jam transfer, it is not necessary to clear the external data register. The gates driving the external data register are part of the external device and are not supplied by the computer. The data register can contain any number of flip-flops up to a maximum of twelve. If more than twelve flip-flops are involved, two or more transfers must take place. Obviously the strobe pulse shown in Figure 5-10 must occur when the data to be placed in the external data register is held in the accumulator. This pulse therefore must be under computer control to effect synchronization with the operation or program of the computer.
Figure 5-10. Loading a Six-Bit Word into an External Device from the Accumulator
Program Interrupt (PI)
When a large amount of computing is required, the program should initiate operation of an I/O device then continue the main program, rather than wait for the device to become ready to transfer data. The program interrupt facility, when enabled by the program, relieves the main program of the need for repeated flag checks by allowing the ready status of I/O device flags to automatically cause a program interrupt. When the program interrupt occurs, program control transfers to a subroutine that determines which device requested the interrupt and initiates an appropriate service routine.
In the example shown in Figure 5-11, a flag signal from a status flip-flop operates a standard gate with no internal load. When the status flip-flop indicates the need for device service, the inverter drives the Program Interrupt Request bus to ground to request a program interrupt.
Figure 5-11. Program Interrupt Request Signal Origin
If only one device is connected to the PI facility, program control can be transferred directly to a routine that services the device when an interrupt occurs. This operation occurs as follows, (example in PDP-8 mode):
Tag Address Instruction Remarks 1000 . /MAIN PROGRAM 1001 . /MAIN PROGRAM CONTINUES 1002 . /INTERRUPT REQUEST OCCURS /INTERRUPT OCCURS 0000 /PROGRAM COUNT (PC = 1003) IS /STORED IN 0000 0001 JMP SR /ENTER SERVICE ROUTINE SR 2000 . /SERVICE SUBROUTINE FOR . /INTERRUPTING DEVICE AND . /SEQUENCE TO RESTORE AC, AND 3001 . /RESTORE LINK 1F REQUIRED 3002 RMF /RESTORE MEMORY FIELDS 3003 ION /TURN ON INTERRUPT 3004 JMP I 0000 /RETURN TO MAIN PROGRAM 3003 . /MAIN PROGRAM CONTINUES . 1004 .In most PDP-12 systems numerous devices are connected to the PI facility, so the routine beginning in core memory address 0001 must determine which device requested an interrupt. The interrupt routine determines the device requiring service by checking the flags of all equipment connected to the PI and transfers program control to a service routine for the first device encountered that has its flag in the state required to request a program interrupt. In other words, when program interrupt requests can originate in numerous devices, each device flag connected to the PI must also be connected to the IOS.
Multiple Use of IOS and PI
In common practice, more than one device is connected to the PI facility. In the basic PDP-12, the teletype flags are already connected. Therefore, since the computer receives a request that is the inclusive OR of requests from all devices connected to the PI, the IOS must identify the device making the request. When a program interrupt occurs, a routine is entered from address 0001 in PDP-8 mode (0041 in LINC mode) to sequentially check the status of each flag connected to the PI and to transfer program control to an appropriate service routine for the device whose flag is requesting a program interrupt. Figure 5-12 shows IOS and PI connections for two typical devices.
Figure 5-12. Multiple inputs to IOS and PI Facilities
The following program example illustrates how the program interrupt routine determines the device requesting service (example in PDP-8 mode):
Tag Address Instruction Remarks 1000 . /MAIN PROGRAM 1001 . /MAIN PROGRAM CONTINUES 1002 . /INTERRUPT REQUEST OCCURS /INTERRUPT OCCURS 0000 /STORE PC (PC = 1003) 0001 JMP FLGCK /ENTER ROUTINE TO DETERMINE /WHICH DEVICE CAUSED INTERRUPT FLGCK, IOT 6341 /SKIP IF DEVICE 34 IS REQUESTING SKP /NO - TEST NEXT DEVICE JMP SR34 /ENTER SERVICE ROUTINE 34 IOT 6441 /SKIP IF DEVICE 44 IS REQUESTING SKP /NO - TEST NEXT DEVICE JMP SR44 /ENTER SERVICE ROUTINE 44 IOT 6541 /SKIP IF DEVICE 54 IS REQUESTING SKP /NO - TEST NEXT DEVICE JMP SR54 /ENTER SERVICE ROUTINE 54 . . .Assume that the device that caused the interrupt is an input device (e.g., tape reader). The following example of a device service routine might apply:
Tag Instruction Remarks SR, DAC TEMP /SAVE AC IOT XX /TRANSFER DATA FROM DEVICE /BUFFER TO AC DAC I 10 /STORE IN MEMORY LIST ISZ COUNT /CHECK FOR END SKP /NOT END JMP END /END. JUMP TO ROUTINE TO HANDLE . /END OF LIST CONDITION . . /RESTORE LINK AND OTHER STATUS IF REQUIRED TAD TEMP /RELOAD AC RMF /RESTORE MEMORY FIELDS ION /TURN ON INTERRUPT JMP I 0 /RETURN TO PROGRAMIf the device that caused the interrupt was essentially an output device (receiving data from computer), the IOT then DAC I 10 sequence might be replaced by a TAD I 10 - then - IOT sequence.