PDP-12 User's Manual

Octal code: 6136
Event time: 2, 3
Execution time: 4.25 µsec
Operation: The AC register is cleared and the contents of the Clock Buffer Preset repister are transferred into the AC.

CLCA - Counter to AC

Octal code: 6137
Event time: 1, 2, 3
Execution time: 4.25 µsec.
Operation: The AC register is cleared and the contents of the Clock Counter are transferred to the Buffer Preset reeister. Then the contents of the Buffer Preset register are transferred into the AC.

Incremental Plotter and Control (Type XY12)

Four models of California Computer Products Digital Incremental Recorder can be operated from a Digital Type XY12 Incremental Plotter Control. Characteristics of the four recorders are:

                         Step                              Paper
CCP                      Size               Speed          Width
Model                  (inches)          (steps/minute)   (inches)

563                   0.01 or 0.005          12,000          31
565                   0.01 or 0.005          18.000          12

Instructions for the recorder and control are:

PLPU - Pen Up

Octal code: 6504
Event time: 3
Execution time: 4.5 µsec
Operation: The plotter pen is raised trom the surface of the paper.
Symbol: None

PLPR - Pen Right

Octal code: 6511
Event time: 1 Execution time: 4.5 µsec
Operation: The plotter pen is moved to the right in either the raised or lowered position.
Symbol: None

PLDU - Drum Up

Octal code: 6512
Event time: 2
Execution time: 4.5 µsec
Operation: The plotter paper drum is moved upward. This command can be combined with the PLPR and PLDD commands.
Symbol: None

PLDD - Drum Down

Octal code: 6514
Event time: 3
Execution time: 4.25 µsec
Operation: The plotter paper drum is moved downward.
Symbol: None

PLPL - Pen Left

Octal code: 6521
Event time: 1
Execution time: 4.25 µsec
Operation: The plotter pen is moved to the left in either the raised or lowered position.
Symbol: None

PLUD - Drum Up

Octal code: 6522
Event time: 2
Execution time: 4.25 µsec
Operation: The plotter paper drum is moved upward. This command is similar to the command 6512 except that it can be combined with the PLPL or PLPD commands.
Symbol: None

PLPD - Pen Down

Octal code: 6524
Event time: 3
Execution time: 4.25 µsec
Operation: The plotter pen is lowered to the surface of the paper.
Symbol: None

Program sequence must assume that the end location is known at the start of a routine since there is no means of specifying an absolute pen location in an incremental plotter. Pen location can be preset by the manual controls on the recorder. During a subroutine, the PDP-12 can track the location of the pen on the paper by counting the instructions that increment position of the pen and the drum.

High-Speed Perforated Tape Reader and Control (Type PR 12)

This device senses 8-hole perforated paper or Mylar tape photoelectrically at 300 characters per second. The reader control requests reader movement, transfers data from the reader into the reader buffer (RB), and signals the computer when incoming data is present. Reader tape movement is started by clearing the reader flag. Data is assembled in the Reader Buffer from the perforated tape. The Reader Buffer is transferred into bits 4 through 11 of the accumulator under program control. The reader flag is connected to the computer program interrupt and instruction skip facilities, and is cleared by IOT pulses. The control circuitry for this device is located in the BA12 Option Mounting Panel. Computer instructions for the reader are:

RSF - Skip on Reader Flag

Octal code: 6011
Event time: 1
Execution time: 4.25 µsec
Operation: The reader flag is sensed, and if it contains a binary 1 the content of the PC is incremented by one so that the next sequential instruction is skipped.
Symbol: If Reader Flag = 1, then PC + 1 = > PC

KRB - Read Reader Buffer

Octal code: 6012
Event time: 2
Execution time: 4.25 µsec
Operation: The content of the reader buffer is transferred into bits 4 through 11 of the AC and the reader flag is cleared. This command does not clear the AC.
Symbol: RB V AC_[4:11] = > AC_[4:11]; 0 = > Reader Flag

RFC - Reader Fetch Character

Octal code: 6014
Event time: 3
Execution time: 4.25 µsec
Operation: The reader flag and the reader buffer are both cleared, one character is loaded into the reader buffer from taper and the reader flag is set when this operation is completed.
Symbol: 0 = > Reader Flag; R? Tape Data => RU I = > Reader Flag when done

A program sequence loop to read a character from perforated tape can be written as follows:

            RFC         /FETCH CHARACTEK FROI~1 TAPE
LOOK,       RSF         /SKIP WHEN RU FULL
            JMP   LOOK
            CLA
            RRU         /LOAD AC FROM RE

High-Speed Tape Punch and Control (Type PP 12)

This option consists of a Royal McBee paper tape punch that perforates 8-hole tape at a rate of 50 characters per second. Information to be punched on a line of tape is loaded in an 8-bit punch buffer (PB) from AC bits 4 through 11.The punch flag becomes a 1 at the completion of punching action, signaling that new information may be transferred into the punch buffer, and punching initiated. The control circuitry for this device is located in the BA12 Option Panel. The punch flag is as described for the Teletype unit. The punch instructions are:

PSF - Ship on Punch Flag

Octal code: 6021
Event time: Execution time: 4.25 µsec
Operation: The punch flag is sensed, and if it contains a binary 1 the content of the PC is incremented by one so that the next sequential instruction is skipped.
Symbol: If Punch Flag = 1, then PC + 1 = > PC

PCF - Clear Punch Flag

Octal code: 6022
Event time: 2
Execution time: 4.25 µsec
Operation: Both the punch flag and the punch buffer are cleared in preparation for receiving a new character from the computer.
Symbol: 0 = > Punch Flag, PB

PPC - Load Punch Buffer and Punch Character

Octal code: 6024
Event time: 3
Execution time: 4.25 µsec
Operation: An 8-bit character is transferred from bits 4 through 11 of the AC into the punch buffer and then this character is punched. This command does not clear the punch flag or the punch buffer.
Symbol: AC_[4:11] V PB = > PB

PLS - Load Punch Buffer Sequence

Octal Code: 6026
Event Time 2, 3
Execution Time: 4.25 µsec
Operation: The punch Flag and punch buffer are both cleared, the content of bits 4 through 11 of the AC is transferred into the punch buffer, the character in the PB is punched in tape, and the punch flag is set when the operation is completed.
Symbol: 0 = > Punch Flag, PB; AC_[4:11] = > PB; 1 = > Punch Flag when done

A progrmam sequence to punch a character when the punch buffer is "free" can be written as follows:

FREE,       PSF         /SKIP WHEN FREE
            JMP FREE
            PLS         /LOAD PB FROM AC AND PUNCH CHARACTER

Card Reader and Control (Type CR12)

The Card Reader and Control Type CR12 reads 12 row, 80 column punched cards at a nominal rate of 200 cards per minute. Cards are read by column, beginning with column 1. One select instruction starts the card moving past the read station. Once a card is in motion, all 80 columns are read. Data in a card column is photo- electrically sensed. Column information is read in one of two program selected modes: alphanumeric and binary. In the alphanumeric mode, the 12 information bits in one column are automatically decoded and transferred into the least significant half of the accumulator as a 6-bit Hollerith code. In the binary mode, the 12 bits of a column are transferred directly into the accumulator so that the top row (12) is transferred into AC0 and the bottom row (9) is transferred into AC11. A punched hole is interperted as a binary 1 and no hole is interpreted as a binary 0.

Three program flags indicate card reader conditions to the computer. The data ready flag rises and requests a program interrupt when a column of information is ready to be transferred into the AC. A read alphanumeric or read binary command must be issued within 1.4 milliseconds after the data ready flag rises to prevent data loss. The card done flag rises and requests a program interrupt when the card leaves the read station. A new select command must be issued immediately after the card done flag rises to keep the reader operating at maximum speed. Sensing of this flag can eliminate the need for counting columns, or combined with column counting can provide check for data loss. The reader- not- ready flag can be sensed by a skip command to provide indication of card reader power off, pick failure, a dark check indication, a stacker failure, hopper empty, stacker full, sync failure or light check indication. When this flag is raised, the reader cannot be selected and select commands are ignored. The reader- not- ready flag is not connected to the program interrupt facility and cannot be cleared under program control. Manual intervention is required to clear the reader- not- ready flag. Instructions for the CR8/I are:

RCSF - Skip on Data Ready

Octal Code: 6631
Event Time: 1
Execution time: 4.25 µsec
Operation: The content of the data ready flag is sensed, and if it contains a 1 (indication that information for one card column is ready to be read) the content of the PC is incremented by one so the next sequential instruction is skipped.
Symbol: If Data Ready Flag = 1, then PC + 1 = > PC

RCRA - Read Alphanumeric

Octal Code: 6632
Event Time: 2
Execution Time: 4.25 µsec
Operation: The 6-bit Hollerith code for the 12 bits of a card column are transferred into bits 6 through 11 of the AC, and the data ready flag is cleared.
Symbol: AC_[6:11] V Hollerith => AC_[6:11]; 0 = > Data Ready Flag

RCRB - Read Binary

Octal Code: 6634
Event Time: 3
Execution Time: 4.25 µsec
Operation: The 12-bit binary code for a card column is transferred directly into the AC, and the data ready flag is cleared. Information from the card column is transferred into the AC so that card row 12 enters AC_[0], row 11 enters AC_[1], row 0 enters AC_[2]... and row 9 enters AC_[11].
Symbol: AC V Binary Code = > AC; 0= > Data Ready Flag

RCSD - Skip on Card Done Flag

Octal Code: 6671
Event Time: 1
Execution Time: 4.25 µsec
Operation: The content of the card done flag is sensed, and if it contains a 1 (indication that the card has passed the read station) the content of the PC is incremented to skip the next sequential instruction.
Symbol: If Card Done Flag = 1, then PC + I = > PC

RCSE - Select Card Reader and Skip if Ready

Octal code: 6672
Event Time: 2
Execution Time: 4.25 µsec
Operation: The status of the card reader is sensed. If the reader is ready, the PC is incremented to skip the next sequential instruction, a card is started toward the read station from the input hopper and the card done flag is cleared.
Symbol: If reader flag = 1, then PC + 1 = > PC; 0 = > Card Done Flag

RCRD - Clear Card Done Flag

Octal code: 6674
Event time: 3
Execution time: 4.25 µsec
Operation: The card done flag is cleared. This command allows a program to stop reading at any point in a card deck.
Symbol: 0 = > Card Done Flag

A logical instruction sequence to read cards is:

START,       RCSE           /START CARD MOTION AND SKIP IF READY JUMP NOT RDY   
                            /JUMP TO SUBROUTINE THAT TYPES OUT 
                            /"CARD READER MANUAL INTERVENTION 
                            /REQUIRED" OR HALTS NEXT,
             RCSF           /DATA READY?
             JMP DONE       /NO, CHECK FOR END OF CARD
             RCRA or RCRB   /YES, READ ONE CHARACTER OR ONE 
                            /COLUMN AND CLEAR DATA READY
             DCA I STR      /STORE DATA
DONE,        RCSD           /END OF CARD?
             JMP NEXT       /NO, READ NEXT COLUMN
             JMP OUT        /YES, JUMP TO SUBROUTINE THAT CHECKS
                            /CARD COUNT OR REPEATS AT START FOR
                            /NEXT CARD

No validity checking is performed by the CR12. A programmed validity check can be made by reading each card column in both the alphanumeric and binary mode (within the 1.4 millisecond time limitation), then performing a comparison check.

Before commencing a card reading program, load the input hopper with cards and press Motor Start and Read S Start pushbuttons. The function of the manual controls and indicators are as follows (as they appear from left to right on the card reader):

Control or Indicator                     Function

A - POWER switch        On-Off toggle switch. Applies power to all circuits
                        except drive motor.

B - MOTOR START         Momentary action pushbutton, with separate indicator.
                        Applies power to main drive motor. Motor start is also
                        used as a reset to clear error indicators and therefore
                        will not operate if there is an unreadied condition
                        such as:

                           1. Input hopper is empty.
                           2. Output hopper is full.
                           3. All photo cells are not lit.
                           4. Internal power supplier is not operational.

C - READ START          Momentary action pushbutton, with separate indicator.
                        Causes ready line to go high, which enables card
                        reading under control of the external read command.
                        If read command is open or high, card reading begins
                        immediately at full rated speed.

D - READ STOP           Momentary action pushbutton, with separate indicator.
                        Inhibits further card reading until READ START switch
                        is pressed again. Ready line goes low and READ STOP
                        condition is indicated. Does not stop drive motor.
                        However, a READ STOP condition is indicated anytime
                        the drive motor is stopped.

E - INDICATORS          Several detection circuits are incorporated in the
                        card reader. Whenever any red indicator lights, the
                        drive motor is stopped after allowing the completion
                        of the current card cycle.

1. PICK FAIL Indicator     Lights when a card fails to enter the read station
                           after two successive pick attempts.

2. DARK CHECK Indicator    After the card enters the read station, a check is
                           made at the hypothetical 0th and 81st hole positions
                           to be sure all photocells are dark. If not, the
                           DARK CHECK indicator lights and data outputs are
                           inhibited immediately.

3. STACKER FAIL Indicator  When three cards have passed the read station and
                           none have been stacked, a STACK FAIL is indicated.
                           Prevents more than three cards from being in the
                           track at once.

4. HOPPER EMPTY Indicator  Indicates input hopper is empty.

5. STACKER FULL Indicator  Switch closure detects when approximately 400 cards
                           are in the stacker hopper.

6. SYNC FAIL Indicator     Internal timing signals are derived from an
                           oscillator which is sync'ed to the track speed. If
                           the sync signal is lost, a SYNC FAIL is indicated.

7. LIGHT CHECK Indicator   All photo cells must always be lit except during
                           the time a card is being read. The detector is
                           inhibited each time a card enters the read station
                           until position (count of) 84. If a card fails to
                           leave the read station by this time, a LIGHT CHECK
                           is indicated.

Digital-To-Analog Converter (Type AA01A)

The general- purpose Digital- to- Analog Converter Type AA01A converts 12-bit binary computer output numbers to analog voltages. The basic option consists of three channels, each containing a 12-bit digital buffer register and a digital-to-analog converter (DAC). Digital input to all three registers is provided, in common, by one 12-bit input channel which receives bussed output connections from the accumulator. Appropriate precision voltage reference supplies are provided for the converters.

One IOT microinstruction simultaneously selects a channel and transfers a digital number into the selected register. Each converter operates continuously on the content of the associated register to provide an analog output voltage.

Type AA01A options can be specified in a wide range of basic configurations; e.g., with from one to three channels, with or without output operational amplifiers, and with internally or externally supplied reference voltages. Configurations with double buffer registers in each channel are also available.

Each single- buffered channel of the equipment is operated by a single IOT command. Select codes of 55, 50, and 57 are assigned to the AA01A, making it possible to operate nine single-buffered channels or various configurations of double-buffered channels. A typical instruction for the AA01A is:

DAL1 - Load Digital-to-Analog Converter 1

Octal Code: 6551
Event Time: 1
Execution Time: 4.25 µsec
Operation: The content of the accumulator is loaded into the digital buffer register of channel 1.
Symbol: AC => DAC1

Random Access Disk File (Type DF32)

Operating through the 3- cycle data- break channel, the DF32 provides 32,768 13-bit words (12 bits plus parity) of storage, and is economically expandable to 131,472 using Expander Disk Type DS32.

Transfer rate of the DF32 is 66 µsec per word; average access time is 16.67 msec for 60-cycle power (20 msec with 50-cycle power).

Two basic assemblies comprise the DF32: the storage unit with read/write electronics, and computer interface logic. The storage unit contains a nickel-cobalt plated disc driven by a hysteresis synchronous motor. Data is recorded on a single disc surface by 16 read/write heads which are in a fixed position. A photo-refiective marker is used on the disc's outer perimeter to denote beginning and end of timing and address tracks.

Disk motor and shaft, read/write data heads, timing and address heads, and photocell assembly are mounted on a rack assembly which permits sliding the unit in and out of a standard Digital Equipment Corporation cabinet.

The disk is designed for rack mounting in a 19 inch relay rack.

Instructions

The command for the disk system are as follows:

DCMA - Clear Disk Memory Address Register

Octal Code: 6601
Event Time: 1
Execution Time: 4.25 µsec
Operation: Clears Memory Address Register, parity error and completion flags. This instruction clears the disk memory request flag and interrupt flags.
Symbol: 0 = > completion flag; 0 = > error flag

DMAR - Load Disk Memory Address Register and Read

Octal code: 6603
Event time: 1, 2
Execution time: 4.25 µsec
Operation: The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to read information from the disk into the specified core location. Clears parity error and completion flags. Clears interrupt flags.
Symbol: AC_[0:11] -> DMA_[0:11]; 0 = > completion flag; 0 = > error flag

DMAW - Load Disk Memory Address Register and Write

Octal Code: 6605
EventTime: 1, 3
Execution Time: 4.25 µsec
Operation: The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to write information into the disk from the specified core location. Clears parity error and completion flags. Clears interrupt flags. Data break must be allowed to occur within 66 µsec after issuing this instruction.
Symbol: AC0-11DDMA0-11; AC_[0:11] -> DMA_[0:11]; 0 = > completion flag; 0 = > error flag

DCEA - Clear Disk Extended Address Register

Octal Code: 6611
Event Time: 1
Execution Time: 4.25 µsec
Operation: Clears the Disk Extended Address and memory address extension register.
Symbol: 0 = > Disk Extended Address Register; 0 = > Memory Address Extenstion Register

DSAC - Skip on Address Confirmed Flag

Octal Code: 6612
Event Time: 2
Execution Time: 4.25 µsec ???
Operation: Skips next instruction if address confirmed Flag is a 1. Flag is set for 16 µsec (AC is cleared).
Symbol: If address confirmed flag = 1, then PC + 1 => PC

DEAL - Load Disk Extended Address

Octal code: 6615
Eventtime: 1, 3
Execution time: 4.25 µsec
Operation: The disk extended address and memory address extension registers are cleared and loaded with the track address data held in the AC.
Symbol: AC,~, = > Core Memory Extension; AC,_, = > Disk Address Extension 32K, 64K, 96K, 128K AC, ,_,, used in DEAC instruction (See NOTE)

DEAC - Read Disk Extended Address Register

Octal code: 6616
Event time: 2, 3
Execution time: 4.25 µsec
Operation: Clear the AC then load the contents of the disk extended address register into the AC to allow program evaluation. Skip next instruction if address confirmed flag is a 1.
Symbol: Disk Address Extension 32K, 64K, 96K, 128K = > AC,_,; Core Memory Extention = > AC,_,; Photo-cell sync mark = > AC, (Available 200 ~sec); Data Request Late flag = > AC,; Non-existent or Write Lock switch on = n AC,, Parity Errors= > AC, 1

NOTE

For the DEAL and DEAC Instructions, refer to the diagrams shown below.

      +--------------+-------------------------+
      |              |        ACCUMULATOR      |      DISC
      |   BITS 1-5   |    (LOW ORDER 12 BITS)  |     ADDRESS
      |  (DEAL INST) |    0-11 of DMAW or DMAR |     (17 BIT)
      +--------------+-------------------------+

      +--------------+-------------------------+
      | FIELD BITS   |                         |     CURRENT ADDRESS
      |   6-8        |        CELL 7751        |    (MEMORY) ADDRESS
      | (DEAL Inst)  |     (CURRENT ADDRESS)   |         (15 BIT)
      +--------------+-------------------------+

DFSE - Skip on Zero Error Flag

Octal code: 6621
Event time: 1
Execution time: 4.25 µsec
Operation: Skips next instruction if parity error, data request late, or write lock switch flag is a zero. Indicates no errors.
Symbol: If Parity Error flag = 1, then PC + 1 = > PC; If Data Request Late flag = 1, then PC + 1 = > PC; If Write Lock Switch flag = 1, then PC + 1 = > PC

DFSC - Skip on Data Completion Flag

Octal code: 6622
Event time: 2
Execution time: 4.25 µsec
Operation: Skips next instruction if the completion flag is a 1. Indicates data transfer is complete.
Symbol: If Completion flag = 1, PC + 1 = > PC

DMAC - Read Disk Memory Address Register

Octal code: 6626
Event time: 2, 3
Execution time: 4.25 µsec
Operation: Clears the AC then loads contents of the Disk Memory Address register into the AC to allow program evaluation. During read, the final address will be the last one transferred.
Symbol: DMA_[0:11] = > AC_[0:11]

The computer can handle 12 bits, therefore, the high order bits for Disk and Memory addresses are manipulated by the DEAL and DEAC instructions. Low order bits are manipulated in the accumulator (AC).

The Disk address is a 17 bit value. Bit 1 of the DEAL and DEAC instructions is the most significant bit. The Memory address is a 17 bit value. Bit 6 of the DEAL and DEAC instructions is the most significant bit.

Note that the Word Count 7750 is the 2's complement of the number of words to be transferred and that the Disk address is the desired starting address. The Memory or Current address (7751) is the desired address -1.

NOTE

Write Lock Switch status is true only when disk module contains write command. The non- existent disk condition will appear following the completion of a data transfer during read, where the address acknowledged was the last address of a disc and the next word to be addressed falls within a non- existent disk. The completion flag for the data transfer is set by the non- existent disk condition 15 microseconds following the completion flag for this data transfer is set by the non- existent disk condition 16 microseconds following the data transfer.

DF32 Software

DF32 Disk System, available with PDP-12, is a fast convenient keyboard oriented monitor which will enable the user to efficiently control the flow of programs through his PDP-12. This system is modular and open ended, allowing the user to build the software components required in his environment. The user may specify the system device (Disk or LINCtape), the amount of core, number of disks available and the number, name and size of his resident system programs.

Disk Memory System (Type RF08, RS08)

The RF08 control and RS08 disk combine as a fast, low- cost, random access bulk storage package for the PDP-8, PDP-8/I and PDP-12 computers. One RS08 and RF08 provide 262,144 13-bit words (12 bits plus parity) of storage. Up to four RS08 disks can be added to the RF08 control for a total of 1,048,576 words of storage.

Data transfer rate on 60 Hz power is 16.2 microseconds per word or 20 microseconds per word on 50 Hz. Data transfer is accomplished through the three- cycle break system of the PDP-8 or PDP-8/I.

Average access time with a 60 Hz disk is 16.67 milliseconds or 20 milliseconds at 50 Hz power. Worst case access time is 33 milliseconds on 60 Hz power or 40 milliseconds on 50 Hz power.

The RS08 disk unit contains a nickel- cobalt plated disk driven by a hysteresis synchronous motor. Data is recorded on a single disk surface by 128 fixed read/write heads.

The RF08 and RS08 are designed for rack mounting in a standard 19 inch DEC cabinet.

DF32 Programming Compatibility

The input-output transfer instructions for the RF/RS08 Disk Memory system are identical with the input- output transfer instructions for the Type DF32 Random Access Disk file with the following exceptions:

DEAL - Load Disk Extended Address

Octal code: 6615
Execution time: 4.25 µsec
Operation: When used in the RF/RS08 Disk Memory system this IOT instruction does not transmit the extended disk address bits for addressing beyond 32K. Instead, accumulator bits AC_[3],AC_[4], and AC_[5] are assigned to enable or disable conditions on the program interrupt line. The accumulator is cleared after this instruction has been executed.

DEAC - Read Disk Extended Address Register

Octal code: 6616
Execution time: 4.25 µsec
Operation: When used in the RF08 Disk Memory system this IOT instruction does not read extended address bits AC_[1] through AC_[5] into the accumulator. These bits are assigned to examine the status of the interrupt enable. In addition accumulator bit AC_[2] indicates the status of Write Lock and accumulator bit AC_[10] shows non- existent disk conditions only. Accumulator bit AC_[1] shows the condition of Data Request Enable, which is used for maintenance purposes.

DFSE - Skip Old Zero Error Flag

Octal code: 6621
Execution time: 4.25 µsec
Operation: When used in the RF08 and RS08 Disk Memory system, this IOT will cause a skip to be returned to the computer on error instead of no error. Non- existent disk has been included as an error-skip condition.

DISR - Skip Error or Completion Flag

Octal code: 6623
Execution time: 4.25 µsec
Operation: This is a new skip instruction added to the RF08 and RS08 Disk Memory system. This IOT will return a skip to the computer if either the error or completion flags or both are raised.

The DF32 maintenance instruction IOT 663X is not assigned to the RF08 system.

DCIM

Octalcode: 6611
Event time: 1
Execution time: 4.25 µsec
Operation: Clear the disk interrupt enable and core memory address extension registers.

DSAC

Octal code: 6612
Event time: 2
Execution time: 4.25 µsec
Operation. Maintenance Instruction Skip next instruction if the Address Confirmed flag is a 1. (AC is cleared.)

DIML

Octal code: 6615
Event time: 1, 3
Execution time: 4.25 µsec
Operation: Clear the interrupt enable, and memory address extension register. Then load the interrupt enable and memory address extension registers with data held in the accumulator Then clear AC.

DIMA

Octal code: 6616
Event time: 2, 3
Execution time: 4.25 µsec
Operation: Clear the accumulator. Then load the contents of the status into the accumulator to allow program evaluation.

-- To be done --

DFSE

Octal code: 6621
Event time: 1
Execution time: 4.25 µsec
Operation: Skip next instruction if there is a Parity Error, Data Request Late, Write Lock Status, or Non- Existent Disk flag set.

DFSC

Octal code: 6622
Event time: 2
Execution time: 4.25 µsec
Operation: Skip next instruction if the Completion flag is a 1 (data transfer complete).

DISK

Octal code: 6623
Event time: 1, 2
Execution time: 4.25 µsec
Operation: Skip next instruction if the Error or Completion flags or both are set.

DMAC

Octal code: 6626
Event time: 2, 3
Execution time: 4.25 µsec
Operation: Clear the accumulator. Then load the contents of the Disk Memory address register into the accumulator to allow program evaluation. This instruction must be issued when the completion flag is set.

DCMA

Octal code: 6601
Event time: 2
Execution time: 4.25 µsec
Operation: Clear the Disk Memory Address register, and all other isk and maintenance flags except interrupt enable.

DMAR

Octal code: 6603
Event time: 1, 2
Execution time: 4.25 µsec
Operation: Load the low order 12 bits of the Disk Memory Address with information (initial address) in the accumulator. Then clear the AC. Begin to read information from the disk into the specified core location. Clear parity error and completion flags. Clear interrupt flags. IOT 6605, see below.

During Read, the final address status is the last address transferred + 1.

When reading the last address of the last available disk the non-existent flag is raised in coincidence with the completion flag.

DMAW

Octal code: 6605
Event time: 1, 3
Execution time: 4.25 µsec
Operation: Load the low order 12 bits of the Disk Memory Address with information (initial address) in the accumulator (AC). Then clear the AC. Begin to Write information onto the disk from the specified core location. Clear parity error and completion flags. Clear interrupt flags.

During Write, the final address status is the last address transferred.

Write Lock Switch status is true only when the disk module contains a Write Command.

-- To be done --

DMAR

Octal code: 6603
Event time: 1, 2
Execution time: 4.25 µsec
Operation: If given during photocell time the read or write operation can begin at Disk Memory Address 0000 without latency due to logic- disk sync. time as is the case if given at any other time. However, in all cases, if the read or write operation is to be on an odd track 1, 2, 5, etc., bit 0 of the AC must be in the one state at the time the DMAR or DMAW is given, as bit 0 of the Disk Memory Address is the first bit of the track address.

DMAW

Octal code: 6605
Event time: 1, 4
Execution time: 4.25 µsec
Operation: If given during photocell time the read or write operation can begin at Disk Memory Address 0000 without latency due to logic- disk sync. time as is the case if given at any other time. However, in all cases, if the read or write operation is to be on an odd track 1, 2, 5, etc., bit 0 of the AC must be in the one state at the time the DMAR or DMAW is given, as bit 0 of the Disk Memory Address is the first bit of the track address.

DMMT

Octal code: 6646
Execution time: 4.25 µsec
Operation: For maintenance purposes only with the appropriate maintenance cable connections and the disk disconnected from the RS08 logic the following standard signals may be generated by IOT 646 and associated AC bits. AC is cleared. The maintenance register is initiated by issuing an IOT 601 command.

AC11(1)	Track A Pulse
AC10(1)	Track B Pulse
AC9(1)	Track C Pulse
AC8(1)	DATA PULSE (DATA HEAD #0)
AC7(1)	+1 Photocell
AC0(1)	+1 DBR

Setting DBR to a 1 causes Data Break Request in computer.

NOTE
TAP must be generated to strobe track B signal into address comparison network.

DCXA

Octal code: 6641
Execution time: 4.25 µsec
Operation: Clear the high order 8 bit disk address register.

DXAL

Octal code: 6643
Execution time: 4.25 µsec
Operation: Clear the high order 8 bits of the Address register. Then load the Disk Address register from the data held in the accumulator. Then clear the AC.

-- To be done --

DXAC

Octal code: 6645
Execution time: 4.25 µsec
Operation: Clear the accumulator the nload the contents of the High Order 8 bit Disk Address register into the PDP accumulator.

-- To be done --

Disk Address Register - 20 bits

-- To be done --

Programming example

A programming example that writes a block of data onto the disk is shown below. For simplicity, the example assumes that all data and instructions are within the same page, but in actual practice, this may not be true.

	/CALLING SEQUENCE
SUB	JMS WRT			/ JUMP TO WRITE SUBROUTINE
	0			/ CONTAINS WORD COUNT
	0			/ CONTAINS INITIAL CORE MEMORY ADDRESS
	0			/ CONTAINS TRACK AND UNIT NUMBER
	0			/ CONTAINS TRACK ADDRESS
	XXX			/ CONTRINUE WITH MAIN PROGRAM

	/WRITE SUBROUTINE
WRT,	0			/ ENTER WRITE SUBROUTINE
	TAD I WRT		/ FETCH WORD COUNT
	DCA WC			/ DEPOSIT IN WORD COUNT REGISTER
	ISZ WRT			/ INCREMENT POINTER
	TAD I WRT		/ FETCH INITIAL CORE MEMORY ADDRESS
	DCA CA			/ DEPOSIT INTO CURRENT ADDRESS REGISTER
	ISZ WRT			/ INCREMENT POINTER
	TAD I WRT		/ FETCH TRACK AND UNIT NUMBER
	DXAL			/ DEPOSIT INTO REGISTER IN RF08 CONTROL
	ISZ WRT			/ INCREMENT POINTER
	TAD I WRT		/ FETCH TRACK ADDRESS
	DMAW			/ TRACK ADDRESS IO DMA IN DISK;
				/ START
				/ WRITE OPERATION
	DFSC			/ JOB DONE?
	JMP .-1			/ NO, WAIT
	DFSE			/ ANY ERRORS?
	JMP .+2			/ NO, SKIP OVER ERROR EXIT
	JMP ERR			/ YES, TO ERROR SUBROUTINE
	ISZ WRT			/ INCREMENT POINTER TO EXIT ADDRESS
	JMP I WRT		/ EXIT PROGRAM

The calling subroutine must be set up so that the subsequent locations to SUB (SUB+1, SUB+2, etc.) contain the parameters as shown in the comments column.

The JMS WRT instruction causes a subroutine jump to location WRT with the contents of the PC-1 (which contains the symbolic address SUB-1) deposited into location WRT. Since location WRT now contains SUB-1, the first instruction of the subroutine (TAD I WRT) loads the AC with the contents of SUB-1 which is the word count. The word count is then deposited into the WC (Memory Address 7750) register. Similarly, the initial address is deposited into the CA (Memory Address 7751) register. The program then proceeds to set up the EMA and DMA registers and starts the write operation. After the DMAW instruction is issued, the data transfer begins and continues independently of the program; it operated under the control of the data break facility to transfer data. When the transfer is complete, the DCF (Data Complete Flag) comes up and, when sensed by the DFSC control, passes to the DFSE instruction. DFSE then senses for errors, and if any, control jumps to an error or diagnostic (not shown) routine. If no errors, control exits from the subroutine back to the main program to resume main processing.

It should be noted that since the data transfer operates independently of the program, the subroutine could be exited following the DMAW instruction. An interrupt subroutine could handle the post data transfer processing since the DCF and ERROR FLAGS generated an interrupt.

An identical program could handle data transfers for a read operation except that the DMAW instruction is replaced by the DMAR instruction.

Specifications:

Storage Capacity	Each RS08 stores 262,144 13-bit words (12 plus
			one event parity bit)

Disks			Four RS08's may be controlled by one RF08 for
			1,048,576 words.

Data Transfer Path	3-Cycle Break		Address Locations
						7750 Word Count
						7751 Memory Address

Data Transfer Rate	60 Hz Power		50 Hz Power
			16.2 uSec per word	20 uSec per word
Minimum Access Time	258 uSec		320 uSec
Average Access Time	16.9 mSec		20.3 mSec
Maximum Access Time	33.6 mSec		40.2 mSec
Program Interrupt	33 Milliseconds Clock Flag
			Data Transmission Complete Flag
			Error Flag

Write Lock Switches	Eight switches per disk capable of locking out
			any combination of eight 16,384 word blocks in
			addresses 0 to 131,071.

Data Tracks		128

Words Per Track		2048

Recording Method	NRZI

Density			1100 BPI Maximum

Timing Tracks		3 plus 3 spare

Operating Environment	Recommended temperature 65° to 90°F. Relative
			humidity 20% to 80%. No condensation storage or
			operating.

Vibration/Shock		Good isolation is provided. Vibrating, shaking or
			rocking of the cabinet with large, low frequency
			displacements can cause data errors. For example,
			hand fork lift trucks operating on wooden floors
			cause excessive vertical displacements which could
			cause errors. The RS08 is not designed for aircraft
			of shipboard mounting.

Heat Dissipation	RF08: 150 watts
			RS08: 500 watts

A.C. Power Requirements	115 +/- 10 VAC, single phase, 50 +/- 2 or 60 +/- 2 Hz

RS08:			Motor start 5.5 amps for 20 +/- 3 sec. Motor run
			4.0 amps continuous.

Line Frequency Stability	Maximum line frequency drift 0.1 Hz/sec. A
			constant frequency motor-generator set or static
			AC/AC inverter should be provided for installations
			with unstable power sources.

Reliability		Six recoverable errors and one non-recoverable error
			in 2 x 109 bits transferred. A recoverable
			error is defined as one that occurs only once in
			four successive reads. All other errors are non-
			recoverable. On-off cycling the RS08 is not
			recommended. The RS08 motor control operates
			independently of the computer power control, thus
			eliminating on-off cycling except for power failures.

Cabinet			A dedicated H950 cabinet is designed to accomodate
			one RF08, up to two RS08's and power supplies. Two
			additional RS08's can be mounted in a second H950.
			Other equipment should not be mounted in disk
			cabinets.

Functional Description

The Type TC50 will control the operation of a maximum of eight digital magnetic tape transports, Types TU20 and TU20A. The Type TC58 interfaces to and uses the PDP-12 3-cycle data break facility for transfer directly to or from system core memory and magnetic tape. The tape transports offer industry- compatible (or IBM- compatible) in both 7 and 9 channel tape transports whth the following characteristics:

			Tape Speed		Densities
	Transport	  (ips)			 (bpi)

     TU20 (7-channel)	   45		       200/556/800
     TU20A (9-channel)	   45			   800

Transfers are governed by the in-memory word count (WC) and current address (CA) register associated with the assigned data channel (memory locations 32₈ and 33₈). Since the CA is incremented before each data transfer, its initial contents should be set to the desired initial address minus one. The WC is also incremented before each transfer and must be set to the 2's complement of the desired number of data words to be transferred. In this way, the transfer which causes the word count to overflow (WC becomes zero) is the last transfer to take place. The number of IOT instructions required for the TYPE TC58 is minimized by transferring all necessary control data (i.e., unit number, function, mode, direction, etc.) from the PDP-12 accumulator (AC) to the control using IOT instructions. Similarly, all status information (i.e. status bits, error flags, etc.) can be read into the AC from the control unit by IOT instructions.

During normal data reading, the control assembles 12-bit computer words from successive frames read from the information channels of the tape. During normal data writing, the control disassembles 12-bit words and distributes the bits so they are recorded on successive frames of the information channels.

Instructions

The commands for the Magnetic Tape Control System are as follows:

MTSF Skip on Error Flag or Magnetic Tape Flag

Octal code: 6701
Event time: 1
Execution time: 4.25 µsec
Operation: The status of the error flaf (EF) and the magnetic tape flag (MTF) are sampled. If either or both are set to 1, the content of the PC is incremented by one to skip the next sequential instruction.
Symbol: If MTF or EF = 1, PC + 1 => PC

MTCR Skip on Tape Control Ready

Octal code: 6711
Event time: 1
Execution time: 4.25 µsec
Operation: If the tape control is ready to receive a command, the PC is incremented by one to skip the next sequential instruction.
Symbol: If tape unit ready, PC + 1 => PC

MTAF Clear Registers, Error Flag, and Magnetic Tape Flag

Octal code: 6712
Event time: 2
Execution time: 4.25 µsec
Operation: Clears the status and command registers, and the EF and MTF if tape control is ready. If tape control not ready, clears MTF and EF flags only.
Symbol: If tape control is ready, 0 => MTF, 0 => EF, 0 => command register
If tape control not ready, 0 => MTF, 0 => EF

Inclusive OR Contents of Accumulator

Octal code: 6724
Event time: 3
Execution time: 4.25 µsec
Operation: Inclusively OR the contents of the command register into bits 0-11 of the AC.
Symbol: AC V command register => AC Automatic Magnetic Tape Control

INT ENB EX EX CLOCK MEM MEM EX MEM Enn COMPL INTERRupT I,,,,..,un~vl\ / 1N1 C""Y' IC~TE~ES~OONRI( ~ ST~TUS REG I I REGISTER i""""" pRoCESsoR MEM MEM SEL flELD 5-80 Write - A word in memory is written on tape with format shown below:

rUTERPL ~RITI BITOF IXIPIR~CTER I

X I Y I Y I X I            CH*RACTERI

BIT   O    (          3    4---------------- (1

8-THESE BITS ARE IGNORED

Read - A word is read into memory from tape with the format shown below:

LPITERPIL PP~ITY slT OF CHP.RP~CTER 1

x I x I x I P1 I             CHP~RPICTER(

BIT   O     1     2     3    4-

Read/Compare - A direct comparison of the characters on tape is made with those in memory. The parity bit is ignored, as are bits 0-3 in each memory word.

Core Dump Mode - This mode is used only with 9-track transports. It is entered by setting bit 4 of the command register.

Core dump mode permits the dumping of complete memory words in the form of two six-bit characters. The format is:

CHAR~CTERI         I        CH*R*CTERL

BITS   0-------------5    6  ----------~11

This is accomplished by only utilizing 7 of the 9 tracks on the tape.

Tape written in CORE DUMP MODE, must be READ (READ/COMPARE) in the same mode. These operations are the same as for a 7-track transport.

Magnetic Tape Transport, Type TU20A (9-Channel)

The Type TU20A is a digital magnetic tape transport designed to be compatible with the Type TC58 Magnetic Tape Control. The transport operates at a speed of 45 inches per second and a density of 800 bpi. The maximum transfer rate is 36,000 eight- bit characters per second. Standard nine- channel 18hl- compatible tape format is used. The specifications for the unit are as follows:

Format: NRZI. Eight data bits plus on parity bit. End and loadpoint sensing compatible with IBM.

Tape: Width of 0.5 inch length of 2400 ft. (1.5 mil.). Reels are 10.5 in., IBM-compatible, with file protect (WRITE LOCK) ring.

Heads: Write-read gap of 0.150 in. Dynamic and static skew is less than 14 µsec.

Tape Specifications: 45 IPS speed. Rewind time is less than 5 msec. Start distance is 0.080 in. (+0.035,-0.025 in.). Stop time is less than 1.5 msec. Stop distance is 0.045 in. (~0.015 in.).

Density: 800 BPI. Maximum transfer rate is 36 kHz.

Transport Mechanism : Pinch roller drive; vacuum column tension.

Conln,~: ON/OFF. ON LINE, OFF L.INE, FORWARD, REVERSE, REWIND, LOAD, RESET.

Physical Specifications: Width of 22 1/4 in., depth of 27 1/6 in., height of 69 1/8 in. Weight-600 tbs.

Read (READICOMPAREI Shufdown Delay. 3.6 milliseconds

Write ShuTdown Delay: Approximately 4.5 milliseconds.

General Purpose Multiplexed Analog-to-Digital Converter System (Type AF01A)

The Type AF01A General- Purpose Multiplexed Analog- to- Digital Converter combines a versatile, multi- purpose converter with a multiplexer to provide a fast, automatic, multichannel scanning and conversion capability. It is intended for use in systems in which computers sample and process analog data from sensors or other external signal sources at high rates. The AF01A is used when greater accuracy than provided by the standard AL)12 A-D converter is needed. The Type AF01A option is used with the PDP-12 to multiplex up to hCanalog signals and to convert the signals to binary numbers. Analog data on each of 64 channels can be accepted and converted into 17-bit digital numbers 420 times per second.*

Swtching point accuracy in this instance is 99.975 per cent, with an additional quantization error of half the digital value of the LSB.

*Conversion rate = [(35 +2) 10-6)((14)1-1 = 420 cycles/sec.
                 = 1(9 + 2)(10-6)(h4)1-1 = 1420 cycles/sec

A/D Converter Specifications

The Type AF01A has a successive approximation converter that measures a 0 to 10 volt analog input signal and provides a binary output indication of the amplitude of the input signal. The characteristics of the A/D converter are as follows:

Accuracy and Conversion Times: See Table 5-4 (includes all linearity and temperature errors)

Converter Recovery Time: Zero

Input and input impedance: 0 to -10v at 10 megohms standard. Input scaling may be specified using the amplifier or sample and hold options (sec Table 1)

Input Loading: +] ~A and 125 pf for 0 to -10v input signal.

Output: Binary number of 6 to ] 2 bits, with negative numbers represented in ?'! complement notation. A Ov input gives a 40008;a -5v input a 0000a and a -1Ov (minus 1 LSB*) input gives 3777n number.

*LSB, least significant bit

Provision is made for using the Type A400 Sample and Hold Amplifier (AH02 option) between the multiplexer output and A/D converter input to reduce the effective aperture to less than 150 nsec. The Type A400 may also be used to scale the signal input to accept ~10v, ~5v, or O to +10v. The Type A200 amplifier (AH03 option) may he substituted for the Type A400 to accomplish the same signal scaling without reducing the effective aperture. Both the AH02 and AH03 options may be used to obtain high input impedance and small aperture. (See Table 5-3.)

Multiplexer Specifications

The multiplexer can include from 1 to 16 Type A]2 I Switch Modules. Each module contains four single-pole, high speed, insulated gate FET switches with appropriate gating. The Type A121 Switches are arranged as a hil-channel group of series- switch single- pole switches with a separate continuous ground wire for each signal input. The switched signal input wire and the continuous ground for each channel are run as twisted pairs to the input connectors mounted on the rear panel. The continuous grounds for all channels are terminated at the high quality ground of the AF01A System. Specifications (measured at input connector) are as follows:

Input Operating Signal Voltages: + 10v to -10v

Current: 1 mA

On Resistance: 450 ohm (max)

Voltage Offset: 0

"Off Leakage": 10 nA (max)

Capacitance: 10 pf(max)

Speed:

10% Input to within 2~s I LSB* of output

Operate Time: The time required to switch from one channel to another is 2 ~s to within 1 LSB of the final voltage. This time is preset within the control and starts when a set or index command is received.

Operation

The Type AF01 System may be operated in either the random or sequential address modes. In the random address mode, the control routes the analog signal from any selected channel to the A/D converter input. In the sequential address mode, the multiplexer control advances its channel address by one each time an index command is received. After indexing through the maximum number of channels implemented, the address is returned to 0. When using sequential operation, the conditioning levels for random addressing are ignored.

The multiplexer switch settling time is preset within the control to initiate the conversion process automatically after a channel has been selected in either the random or sequential address mode. Two separate A/D Convert I/O Transfer Commands may also initiate one or more conversions on a currently selected channel.

A/D conversion times are increased by 2 ~sec when multiplexer channels are switched to allow for settling time of the analog signal at the multiplexer output. Conversion times are increased an additional 3 ~sec when AH03 is used. These times are added to the conversion times shown in Table 5-4 under selected channel conversion time which is the only time required for each successive conversion on a selected channel.

When the Type AH02 Sample and Hold option is required, the multiplexer switch settling time and the sample and hold acquisition time are overlapped. The total conversion and switching time is increased by 10~sec. (See A400 specifications).

A/D CONVERTERIMULTIPLEXER CONTROLS

DESIGNATION                              FUNCTION

WORD LENGTH:           Rotary switch used to select digital word length or conversion accuracy.
                       Refer to Table 5-4 for corresponding conversion times.

POWER ON/OFF:          Applies 117 Vac power to internal power supplies. CLR                      Clear multiplexer channel-address registers: i. e.. selects an;llog chanllel O for conversion.

INDEX:                 Advances multiplexer channel-address register by one each time it is depressed, enabling manual addressing of channels (up to 64) in sequential mode. Returns address to zero when maximum value is reached.

AD(`:                  Starts conversion of the analog voltage on the selected channel to a binary number when depressed.

A/D CONVERTER:         Indicates binary contents of A/D converter register.

MULTIPLEXER            indicates binary contents of multiplexer channel-address register.

POWER:                 Indicates ON/OFF status.

TABLE 5-3. INPUT SIGNAL SCALING

                       INPUT        INPUT     BINARY    OPTION CONFIGURATION GAIN    SIGNAL    IMPEDANCE  OUTPUT  DESIGNATION

Standard                       O            IOmeg.         4000,

 5           10 meg.        0000,       STD --10           IOmeg.          3777,

Sample&         1       +5          10K         37775 Hold               I         O            IOK           00008        AHO2 5          IOK         4000,

Sample&         %      +10         IOK         3777, Hold               1/2        O            ]OK           0000,       AHO2 %         10          IOK           4000,

                  +1          +5            >100 meg.      4000, Amplifier         +1          O            >100 meg.       0000,        AHO3 +1           5           >100 meg.      3777,

                          +10         >100 meg.     4000, Amplifier          +%         0            >100 meg.      0000,        AHO3 +%        10       >100 meg.     3777,

Amplifier            1         +5  +10     >100 meg.      3777,        AHO3 and Sample       or         O or O      >100 meg.      0000,        & & Hold             K        --5  -]O    >100 meg.      4000,        AH02

Note: Unipolar signals (O to +5, or O to +10v) may also be specified with either the AHO3 or AHOZ option.

TABLE 5-4. SYSTEM CONVERSION CHARACTERISTICS**

          Random

Selected                      AH03       AH02       AH02 or Channel      Sequential      MPX        MPX       AH03

        (MPX& *ZiD)    A/D      P~ID    MPX &A/D
(aiD)

Word Length        Max
                           Conversion  Conversion    Co"ve'sion  Conversion  Conversion (No. of Bits)      Switchirg
          Time       Time      Time       Time       Time Point

Error*     (~"C)       (~"E)**    (IISeC)**     (C(seC)**     (IISec)**

6            ~1.6~        9.0      1].O (9.5)   14.0 (1].0)   19.0 (14.0)   21.0(18.0) 7            ~o.sm       10.5      12.5(1].0)   15.5 (12.5)   20.5 (15.5)   7?.5 (19.5) 8              +0.4'%        1?.0       14.0(12.5)    17.0 (14.0)    ?2.0(17.0)    ?4.0 (21 0) 9             +0.2%·       13.5      15.5 (14.0)   18.5 (15.5)   23.5 (18.5)   25.5 (22.5) 10           ~o. I~      Is.o     20.0 (18.5)   230(20.0)   28.0 (?3.0)   30.0 (27.0) II             ~0.05'j~      25.0      270          30.0          35.0          37.0 12           ~0.0?5~    35.0     37.0        40.0        45.0        47.0

 *~K LSB for quantiring error.
**lf system is to operate at less than IO bits continuously, conversion times may be reduced to times shown in par entheses.

Programming

Programmed control of the converter/ multiplexer by the PDP-12 is accomplished with the 107 instructions listed below. PDP-12 selects the converter/ multiplexer with two device selection codes, depending upon whether conversion of multiplexing functions are being selected; 53, and 54,. The converter/ multiplexer interprets the device selection code to enable execution of the IOP command pulse generated by the IOT instruction.

ADSF - Skip on A-D Flag

Octal code: 6531
Event time:
Execution time: 4.25 µsec
Operation: The A-D converter flag is sensed, and if it contains a binary 1 (indicating that the conversion is complete) the content of the PC is incremented by one so that the next instruction is skipped.
Symbol: If A-D Flag = 1, then PC + 1 = > PC

ADCV - Convert Analog Voltage to Digital Value

Octal code: 6532
Event time: 2
Execution time: This time is a function of the accuracy and word length switch setting as listed in Table 2.
Operation: The A-D converter flag is cleared, the analog input voltage is converted to a digital value. and then the A-D converter flag is set to 1. The number of binary bits in the digital- value word and the accuracy of the word is determined by the preset switch position.
Symbol: 0 = > A-D Flag at start of conversion, then 1 = > A-D Flag when conversion is done.

ADRB - Read A-D Converter Buffer

Octal code: 6534
Event time: 3
Execution time: 4.25 µsec
Operation: The converted number contained in the converter buffer (ADCB) is transferred into the AC left justified; unused bits of the AC are left in a clear state, and the A-D converter flag is cleared. This command must be preceded by a CLA instruction.
Symbol: ADCB = > AC; 0 = > A-D Converter Flag

ADCC - Clear Multiplexer Channel

Octal code: 6541
Event time:
Execution time: 4.25 µsec
Operation: The channel address register (CAR) of the multiplexer is cleared in preparation for setting of a new channel.
Symbol: 0 = > CAR

ADSC - Set Multiplexer Channel

Octal code: 6542
Event time: 2
Execution time: 4.25 µsec
Operation: The channel address register of the multiplexer is set to the channel specified by bits 6 through 11 of the AC. A maximum of 64 single- ended input channels can be used.

ADIC - Increment Multiplexer Channel

Octal code: 6544
Event time: 3
Execution time: 4.25 µsec
Operation: The content of the channel address register of the multiplex is incremented by one. If the maximum address is contained in the register when this command is given, the minimum address (00) is selected.
Symbol: CAR + 1 = > CAR

The converter/multiplexer may be operated by the computer program in either the random or sequential addressing mode. In the random addressing mode, the analog channel is selected arbitrarily by the program for digitizing and the resultant binary word is read into the accumulator. A sample program for the random addressing mode is as follows:

       TAD ADDR            /YES GET CHANNEL ADDRESS
       ADSC                /AND SEND TO MULTIPLEXER
       ADCV                /CONVERT A TO D
       ADSF                /SKIP ON A/D DONE FLAG
       JMP. -1             /WAIT FOR FLAG
       ADRB                /AND READ INTO AC

In the sequential address mode, the program advances the multiplexer channel- address register to the next channel each time an analog value is converted and read into the accumulator.

Should the converter/multiplexer be operated in the interrupt mode, the computer will be signaled each time that a binary word is ready, enabling the system to use processor time more efficiently.

Amplifier, Sample and Hold Options for AFOIA

The AH03 consists of a DEC amplifier (part ~ 1505379) mounted on an A990 Amplifier Board with appropriate scaling networks and gain trim and balance potentiometers.

Open loop gain                                2 x 106 Rated output voltage                                (@ 10 ma) +i iv Frequency response Unity Gain, small signal                       10 me Full output voltage                                300 kc Slewingrate                                    30v/~csec Overload recovery                              200 ~sec

Input voltage offset                          Adjustable to 0 Avg vs temp                             20 ~viOC Vs supply voltage                       15 i~vi% Vs time                              10 ~v/day

Input current offset                          ~2 na Avg vs temp                             0.4 na/oC Vs supply voltage                       0.15 na/%

Input impedance Between inputs                 6 meg Common mode                      500 meg

Input voltage                                  ~15v Max common mode                    ~10v Common mode rejection                  20,000

Power

Voltage                                        +15 to 16v Current at rated load                            35 ma

A400 (standard gain options) Acquisition time to 0.01% (full-scale step) <12 ~sec Aperture time <150 nsec Hold inaccuracy (droop) <1 mv/msec Temperature coefficient 0.1 mvimsecioC Gain (negative) 1.0 0.5 Input range (volts) ~5.0 +10.0 Impedance 10K IOK Output voltage O to -10v Impedance <1.0 ohm

Guarded Scanning Digital Voltmeter (Type AF04A)

Descrpition

The Type AF04A is a guarded scanning digital voltmeter system, with wide dynamic range and high common- mode rejection, and fully capable of expansion to 1000 channels. The Type AF04A is used with a PDP 12 computer to multiplex up to 1000 .i-wire analog channels into a ~-decimal-digit (BCD) integrating digital voltmeter. Full scale ranges are from i IO my to ~300v, with automatic ranging, 300 percent over ranging, and a usable 5 ~v resolution. Guarded input construction and active integration assist in attaining an effective common- mode rejection of greater than 140 db at 11I1 frequencies. (Normal-mode rejection is infinite at multiples of power line frequency.)

This system is ideally suited for data acquisition or process monitoring where a wide range of signals requires large dynamic range. The 10-mv range has 0.001 percent resolution and, coupled with excellent noise rejection, allows accurate direct measurement of thermocouples, strain gauges, load cells, and other low-level transducers without additional amplification.

The AFO·1A Voltmeter, operated under program control. is capable of either random channel selection or sequential channel selection. The computer selects either program controlled ranging (for fastest speed) or autoranging, as well as the integration time of the integrating digital voltmeter (IDVM). The digitized data, as well as the current channel address, is read by the computer in either two or three bytes.

A decimal display of the digitized value, including sign and decimal location, is continuously displayed on the front panel. The current channel number is also displayed. Front- panel controls on the digital voltmeter allow manual setting of all the programmed functions. A front- panel control allows continuous display of the internal secondary standard, which can be prewired to a particular channel for reference checking during normal operation. The AF04A Voltmeter System may be manually controlled, completely independent of the computer.

SPECIFICATIONS

Full scale~                                             ]Omv, 1 OOmv, iv, IOvl
                                                 100v, 300v, and automatic ranging Over ranging                            300% on all but highest range Resolution                                      5 ~v (usable), O. I~V(LSB) Accuracy (overall                               ~0.004% of reading worst case with                                 +0.017o of full scale~5~v daily calibration at calibration temperature)

Stability (RMS full scale                           +O.OO~~/day and zero drift) Temperature coefficient                       ~0003~ of reading/oC Full scale                                       +0.002r~ of full scaleioC Zero                                     (~0.006% of full scaleioC on 10 my and iv range) Line voltage stability                          ~0.0005~/10~ change Maximum common-mode voltage            ~300v from power line ground Common-mode rejection (16h.6             > 140 db at all frequencies msec integration period and ]000 ohm-source unbalance)

Normal-mode rejection                        Infinite at multiples of line frequency Input impedance 10, 100, 1000 my                                  1000 meg/v ranges Internal secondary standard Value                                          +1.000v Accuracy                                    ~0.00246 traceable to N.B.S. Stability                                                ~0.005%/month Temperature coefficient                                             negligible

SELECTED RESOLUTION

0.00141                       0.014g                            0.]%

DC Voltage    Maximum            Maximum              Maximum Range          Reading     Resolution    Reading      Resolution        Reading    Resolution

IOmv           30.0000 my     O.l~v        030.000 my     I~v           0030.00 my     IOl~v 100mv         300.00 my      i~cv         0300.00 my     ]Ol~v          00300.0 my     1001~v 1000 my        3000.00 my     IO~v        03000.0 my     ]00~v         003000. my     1 my IOv               30.0000v         100~v         030.000v         Imv              0030.00v         IOmv 100v            300.000v        Imv          0300.00v        10 my           00300.0v        100 my ]000v*        0300.00v      10 my       00300.0v      100mv        000300.v      iv

*1000v range is scanner-limited to 300v peak maximum

SCANNING SPEED

(Programmed Range)

Resolution                    integration               Total                     Scanning Time                  Time                  Speed

0.1%                         1.6                    20 msec                50 ch/sec. 0.01%                     16.6 msec             40 msec               25 chisec. 0.001~                    166.6 msec             188 msec               5 chisec.

Scanning Speed (Auto Range)Add 6-36 msec depending on per-channel voltage span.

Instructions

The I/O transfer (IOT) commands associated with the scanning digital voltmeter system are designed to minimize the computer overhead associated with this option while retaining maximum program controlled flexibility. The IOT instructions are:

VSEL - Select Range and Gate

Octal code: 6542
Event time: 2
Execution time: 4.25 µsec
Operation: The contents of the accumulator are transferred to the AD04A control register as shown below.
Symbol: C(AC) = > C(VCR)

CONTROL WORD 1 (FROM PDP-I2)

0 I  1 1  2 1  3 1  4 1  5 1 a  1  7 1  8 1  9 1 10 1 11

SELECT   I    I    I    I    I     I    1       RANGE       GATE
AC   DC   ~2    F   P    I OPTION                 TIME SCANNER RESET

VCNV - Select Channel and Convert

Octal code: 6541
Event time:
Execution time: 4.25 µsec
Operation: The contents of the accumulator are transferred to the AF04A channel address register as shown below. The analog signal on the selected channel is automatically digitized.
Symbol: C(AC) = > C(VAR)

CONTROL WORD Z (FROM PDP-12)

0   I    1   1    2   1    3   1   4   1    5   1   6   1   7    1    8   1-  9   1   io  I   11

ro'          I           to'          I           100

CHANNEL SELECT

VINX - Index Channel and Convert

Octal code: 6544
Event time: 3
Execution time: 4.25 µsec
Operation: The last channel address is incremented by one and the analog signal on the selected channel is automatically digitized. The contents of the control register is unchanged.
Symbol: VAR + 1 => VAR

VSDR - Skilp on Data Ready

Octal code: 6531
Event time: 1
Execution time: 4.25 µsec
Operation: When the scanning voltmeter has selected a channel and digitized the analog signal, a data ready flag is set. This instruction is used to test for the data ready flag.
Symbol: If Flag = 1, then PC + 1 = > PC

VRD - Read L)ofe a,,d Clear Flag

Octal code: 6532
Event time: 2
Execution time: 1.25 µsec
Operation: The contents of the selected byte of the voltmeter output word is transferred to the accumulator and the data ready flag is cleared. The first data flag after the flag is set, is always byte 1 (see below). Subsequent bytes are program selected using the byte advance command.
Symbol: C(VOR) = > C(AC)

DATA WORD (TO PDP-12) BYTE 1

0  I   1   1   2  1   3  1  4  1   5  1  a   1   7  1   8  1   9  1  io I  11

105     1              104

SIGN      RANGE       OPTION          DIGITIZED VOLTAGE

,6x X=0-7

0 I  1  1  2 1  3 1  4 1  5 1 6  1  7 1  8 1  9 1  io I 11

to'             I              ro'             1              101

DIGITIZED VOLTAGE

0 I  1 1  2 1  3 1  4 1  5 1 a 1  7 1  8 1  9 1  io I 11

100           1             to'           I             100

DIC.ITIZED VOLTAGE                  CURRENT CHANNEL

VBA - Byte advance

Octal code: 6534
Event time: 3
Execution time: 4.25 µsec
Operation: The total data word from the AF04A is 36-bits long. The first data word after the flag is set, is always the twelve most significant bits. The BYTE ADVANCE command requests the next twelve most significant bits. When the data is available, the data ready flag is set again. To select the twelve least significant bits, a second BYTE ADVANCE command is required. When the data is available, the data ready flag is set again.
Symbol: C(VOR,~,,)= > C(VOR,,~,,) or C(VOR,,~,,)= > C(VOR, 4-) i)

VSCC - Sample Current Channel

Octal code: 6571
Event time: Execution time: 4.25 µsec
Operation: The analog signal on the current channel is digitized. This command is not required except when multiple samples are required on any channel. (Using this command on a preselected Channel saves up to 10 milliseconds per sample.)
Symbol: None

5-114 Frequency and Period Measurement Options for AF04A

A separate input permits the IDVM to be used as a frequency counter capable of counting to 2MHz with selectable gate times of 1, 10, and 100 milliseconds, providing measurement resolution of 10Hz. Increased accuracy at low frequencies (to 10kHz with automatic 250% overranging) is accomplished with the period- measurement mode. This mode counts an internal frequency source for 1, 10, or 100 periods of the frequency being measured, thereby providing increased full- scale accuracy. Period readout is in milliseconds.

Frequency and voltage measurements may be made within one scanning cycle by grouping all frequency inputs in one master or slave scanner and all voltage inputs in another master or slave scanner. The output of the scanner may then be connected to the frequency- input connector of the IDVM and the output of the other scanner to the voltage input. One of the optional control word bits is used to program the IDVM for frequency or period measurements.

SPECIFICATIONS

Frequency Measurements

Range:        10Hz to 2MHz

Sensitivity:     100mv rms or  iv pulses, at least 0.3 ~sec wide at 50% points. 100 v rms maximum working voltage.

Input Impedance:   22k ohms shunted by less than 1000 pf, including internal
                   cabling.

Accuracy:     ~1 count + time base accuracy

Time Base:    100 KHz crystal oscillator with initial accuracy of ~0.0005%,
              long-term stability ~0.0001%/wk; temp. coefficient f0.0002%/OC.

Period Mensurements

Range:        i, 10, and 100 period average. Input frequency from 10Hz to 2SkH~
              sine wave or 0.1 pps. to 25,000 pps.

Sensitivity:     100 mv rms or   iv pulses, at least 0.3 ~sec wide at 50%
                 points. 100v rms maximum working voltage.

Input Impedance:   22k ohms shunted by less than 1000pf, including internal
                   cabling.

Accuracy:     ~I count + time base accuracy + trigger error. Trigger
              error < + 0.03% for 100mv rms sine wave with 40db
              signal-to-noise ratio.

Time Base:   100kHz crystal oscillator with initial accuracy of +0.0005%
             long-term stability +0.0001%/wk; temp.  coefficient +0.0002%10C.


SI~:e~r~t~a, 1               0.001&             1                0.01%            (               O.lib

                                         I~uding                    Rladioe   I Relolution Funcuon I  ~m I RFsoluflonl  MB"Olum  I Realufion ) MBLimum

Frequency I 2000.00kHr I    10Hz    I 02000.0kHz I   100Hz   I 002000kHz I    IkHz Period   I 99.9999msec I     O.l~s     I 999.999msec       l.Ol~s    19999.99msec I     IO~s

Information on the following options may be had from your nearest DIGITAL EOUIPMENT CORPORATION Office:

Frequency (period) measurements. AC/ohms/DC Converter Time-of-day clock.
Thumb-wheel data entry panel. Thermocouple reference junctions.
Extended scanner for more than 1000 channels. Special cabinet with roll-out drawer chassis accessibility.