PDP-12 User Handbook (Preliminary)

Foreword

    This HTML version of the PDP-12, Laboratory Instrumentation Computer, "User Handbook" has been prepared by Carl R. Friend with permission from Digital Equipment Corporation. Digital retains copyright to this document.

    The transcriber wishes to recognise and thank Mr. Robert Supnik, V.P. of Digital R&D for his invaluable assistance in this venture.

    This document was prepared with using a mixture of OCR/scanning and manual HTML conversion. I have taken the liberty to correct a few of the original (preliminary) manual's flaws. It is my sincere hope that this document will be of use to others in the future.

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Corporate Copyright Information

DEC-12-GRZA-D

PDP-12
USER HANDBOOK
PRELIMINARY

1st printing April 1969
2nd printing June 1969
3rd printing August 1969
4th printing November 1969

Copyright 1969 © by Digital Equipment Corporation

The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts:

DEC, PDP, FLIP CHIP, FOCAL, DIGITAL, COMPUTER LAB

ABSTRACT

The coverage of the PDP-12 Programmed Data Processor contained in this User's Handbook is preliminary. A final version of the handbook will be available in the near future and can be obtained from your DEC sales office (see Rear Cover) or upon written request from the Digital Equipment Corporation, Maynard, Massachusetts 01754.

PDP-12 Programmed Data Processor

Table of Contents

1. GENERAL DESCRIPTION
   
   
   1. Description
      1. System
      2. Central Processor
      3. Memory
      4. Operating Modes
      5. Input/Output Facilities and Display
   2. Symbols and Abbreviations
   
   
2. CONTROLS AND INDICATORS
   
   
   1. PDP-12 Console Controls and Indicators
   2. Data Terminal Panel
   3. Type VR-12 Oscilloscope
   4. Type TU55 Tape Transport
   5. Model ASR-33 Teletype Controls
   
   
3. LINC MODE PROGRAMMING
   
   
   Section I. ORGANIZATION OF MEMORY
   
   
   1. Program Counter
   2. Instruction and Data Field Registers
   3. Instruction Field Reserved Locations
   4. Data Field Reserved Locations
      
      Section II. MEMORY ADDRESSING METHODS
      
      
   5. Direct Addressing
   6. Indirect Address: B-Class
      1. B-Registers
      2. B-Register Indexing
   7. Addressing, a-Class
      
      Section III. LINC MODE INSTRUCTIONS
      
      
   8. Instruction Formats
   9. Instruction Descriptions
   10. Full-Word Data Transfers
   11. Full-Word Arithmetic
       1. Overflow
       2. Instructions
   12. Full-Word Logic
   13. Full-Word Comparison
   14. Half-Word Operations
       1. Half-Word Addressing
   15. a-Class Operation
   16. Program Control
   17. Shift and Rotate Operations
   18. Skips
   19. Miscellaneous
   20. Console Switches
   21. Mode Control
   22. Memory Addressing Control
       1. Instruction Field Buffer (IB) 5 Bits
       2. Save Field Register (SF) 10 Bits
       3. Memory Control Programming
   23. Program Interrupt
   24. Special Functions
   25. Instruction Trap
       1. Tape Trap
       2. Program Interrupt and Instruction Trap
       
       Section IV. CRT DISPLAY
       
       
   26. Half-Size Characters
   27. Character Set
   28. Point Displays
   29. Character Displays
       
       Section V. DATA TERMINAL PANELS
       
       
   30. Analog Inputs
   31. Relays
       
       Section VI. LINCTAPE
       
       
   32. Organization of Data
   33. Programming
   34. Tape Motion
   35. LINCtape instructions
   36. Extended Operations
       1. Extended Address Format
       2. Extended Units
       3. Tape Interrupt Enable
       4. No Pause Condition
       5. Hold Unit Motion
       6. Mark Condition
       7. Maintenance Mode
       8. Tape Trap
   
   
4. PDP-8 MODE PROGRAMMING
   
   
   Section I. ORGANIZATION OF MEMORY
   
   
   1. Organization
   2. Page 0
   3. Extended Memory
      
      Section II. MEMORY ADDRESSING METHODS
      
      
   4. Direct Addressing
   5. Indirect Addressing
   6. Autoindexing
      
      Section III. PDP-8 INSTRUCTIONS
      
      
   7. Memory Reference instructions
   8. Operate Instructions
      1. Operate Class: Group I
      2. Combined Operations: Group I
      3. Operate Class: Group II
      4. Combined Skips In Group II
      5. Input/Output Transfer Class
      
      
      Section IV. PROGRAM INTERRUPT, PDP-8 MODE
      
      
   9. Operation
   10. Using the Interrupt
       
       Section V. EXTENDED ARITHMETIC ELEMENT
       
       
   11. Operation
   12. EAE Instructions
   13. EAE Programming
       
       Section VI. EXTENDED MEMORY
       
       
   14. Registers
       1. Instruction Field Register (IF), 3 Bits
       2. Data Field Register (DF), 3 Bits
       3. Instruction Field Buffer (IB), 3 Bits
       4. Save Field Register (SF), 6 Bits
       5. Break Field Register (BF), 3 Bits
   15. Instructions
   16. Programming
       1. Auto Indexing
       2. Calling A Subroutine Across Fields
       3. Program Interrupt
   
   
5. INPUT/OUTPUT BUS AND PERIPHERALS
   
   
   1. Programmed Data Transfers and I/O Control
      1. Timing and IOP Generator
      2. Device Selector (DS)
      3. Input/Output Skip (IOS)
      4. Accumulator
      5. Input Data Transfers
      6. Output Data Transfers
      7. Program Interrupt (PI)
   2. Data Break Transfers
      1. Single-Cycle Data Breaks
      2. Input Data Transfers
      3. Output Data Transfers
      4. Memory Increment
      5. Three-Cycle Data Breaks
   3. Interface Design and Construction
      1. PDP-12 Interface Modules
      2. M Series Flip Chip Modules
      3. Construction of Interfaces
      4. IOT Allocations
      5. Interface Connections
   4. Standard I/O Bus Peripherals
      1. Teletype Model 33 ASR and Control
      2. TTY/DATAPhone Interface (DP12)
      3. Teletype Option (Type PT08)
      4. KW12 Real-Time Clock
      5. Incremental Plotter and Control (Type XY12)
      6. High-Speed Perforated Tape Reader and Control (Type PR12)
      7. High-Speed Tape Punch and Control (Type PP12)
      8. Card Reader and Control (Type CR12)
      9. Digital-To-Analog Converter (Type AA01A)
      10. Random Access Disk File (Type DF32)
      11. Disk Memory System (Type RF08, RS08)
      12. Automatic Magnetic Tape Control
      13. General Purpose Multiplexed Analog-To-Digital Converter System (Type AF01A)
      14. Guarded Scanning Digital Voltmeter (Type AF04A)
      15. Frequency and Period Measurement Options for AF04A
   
   
6. PDP-8 PROGRAM LIBRARY
   
   
   1. PDP-12 Programs
   2. PDP-8 Programs
      1. System Programs
      2. Elementary Function Routines
      3. Utility Programs
   3. DECUS Programs
   4. Diagnostic Programs

List Of Illustrations

• 1-1 PDP-12 Programmed Data Processor System, Functional Block Diagram
• 2-1 PDP-12 Operator Console
• 2-2 Power Switch Panel
• 2-3 Relay and Analog Input Panel
• 2-4 Type VR12 Oscilloscope
• 2-5 TU30 Tape Transport Control Panel
• 2-6 ASR-33 Teletype
• 3-1 Memory Bank Segments and Addresses
• 3-2 Direct Address Instruction Format
• 3-3 B-Class Instruction Format
• 3-4 B-Class Format
• 3-5 a-Class and Non-Memory Reference Format
• 3-6 Rotate Left
• 3-7 Rotate Right
• 3-8 Scale Right
• 3-9 QAC Transfer Path
• 3-10 Data Path: IB, IF, DF,and AC
• 3-11 Data Path, RMF instruction
• 3-12 Special Functions
• 3-13 CRT Grid
• 3-14 Display Pattern for DSC
• 3-15 Relay Terminals and Corresponding AC Bits
• 3-16 LINCtape Format
• 3-17 LINCtape Processor Information Path
• 3-18 LINCtape Instruction Format
• 3-19 Extended Operations Buffer Bit Assignments
• 4-1 Organization of Memory, PDP-8 Mode
• 4-2 Memory Reference Instruction Format
• 4-3 Group I Operate Class Instruction Format
• 4-4 Rotation Scheme for RAR, RTR, RAL, RTL
• 4-5 Group II Operate Class Instruction Format
• 4-6 EAE Instruction Format
• 4-7 Shift Path for NMI, SHL
• 4-8 Shift Path for ASR
• 4-9 Shift Path for LSR
• 4-10 Data Path to SF and AC
• 5-1 Logic Symbols
• 5-2 IOT Instruction Decoding
• 5-3 Programmed Data Transfer Interface Block Diagram
• 5-4 Programmed Data Transfer Timing
• 5-5 Generation of IOT Command Pulses by Device Selectors
• 5-6 Typical Device Selector (Device 34)
• 5-7 Use of IOS to Test the Status of an External Device
• 5-8 Accumulator Input or Output
• 5-9 Loading Data into the Accumulator from an External Device
• 5-10 Loading a Six-Bit Word into an External Device from the Accumulator
• 5-11 Program Interrupt RequestSignalOrigin
• 5-12 Multiple Inputs to IOS and PI Facilities
• 5-13 Data Break Transfer Interface Block Diagram
• 5-14 Single Cycle Data Break Input Transfer Timing Diagram
• 5-15 Device Interface Logic for Single-Cycle Data Break Input Transfer
• 5-16 Single Cycle Data Break Output Transfer Timing Diagram
• 5-17 Device Interface Logic for Single Cycle Data Break Output Transfer
• 5-18 Memory Increment Data Break Timing Diagram
• 5-19 Three-Cycle Data Break Timing Diagram
• 5-20 Typical M111/M906 Positive Input Circuit
• 5-21 Typical M516 Positive Bus Receiver Input Circuit
• 5-22 Typical M623/M906 Positive Output Circuit
• 5-23 Typical M660 Bus Driver Output Circuit
• 5-24 M103 Device Selector Logic Circuit
• 5-25 M101 Bus Data Interface Logic Circuit
• 5-26 I/O Bus Configuration
• 5-27 I/O Cable Connections
• 5-28 KW12 Clock Organization
• 5-29 Simplified Input Synchronizer