Data General Corporation
Eclipse S/230 processor

[JPEG image of S-230]

    This machine, a Data General Corporation Eclipse S/230, was rescued from the scrappers in late 1993. It originally functioned as the main processor for a CADD (Computer Aided Design and Draughting) platform produced by Calma Corp. and drove 6 graphics workstations.

    The S/230 is a 16 bit minicomputer with 512 kw of memory and is a descendant of Data General's Nova line. In fact, the I/O bus on this machine is hardware compatible with the Nova's allowing boards to be shared between the machines. This was one of the very last of the Eclipse line to sport a programmer's console .

    The basic architecture is that of the Nova - four accumulators, separate memory and I/O busses, and a basic 32 kw virtual address space. Unlike its earlier Nova cousins, however, this device's ISP (Instruction Set Processor) is microcoded. Perhaps as a direct result of the new architecture, DG's designers went "nuts" with extensions to the Nova instruction set. Taking careful advantage of the fact that (hopefully) no (sane) programmer would ever code the "No Load" and "Never Skip" options together in a single instruction, DG promptly used this combination to produce one of the fatter instruction sets known in minicomputer history.

    The microcode for the standard instruction set is blasted into mask ROM. DG produced an option for this machine called a WCS (Writable Control Store) that enabled users to write their own instructions for the machine thereby taking full advantage of the iron's possible speed (this particular example lacks the option).

    This particular Eclipse contains a Memory Management and Protection (MAP) Unit that expands the physical memory capacity to 512 kw and keeps programs from accessing each other's address space unintentionally. The MAP device works along the lines of modern paging, but does not support "virtual memory" in the modern sense. The memory proper is done in MOS DRAM (Metal Oxide Semiconductor, Dynamic Random Access Memory) and is refreshed at the board level with no intervention required by the CPU.

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